Search

John P. Dulka

Examiner (ID: 18278, Phone: (571)270-7398 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2817, 2895
Total Applications
1000
Issued Applications
819
Pending Applications
77
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11802358 [patent_doc_number] => 09543258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield' [patent_app_type] => utility [patent_app_number] => 15/011311 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2893 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011311 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/011311
Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield Jan 28, 2016 Issued
Array ( [id] => 10795059 [patent_doc_number] => 20160141216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'PROBE PAD WITH INDENTATION' [patent_app_type] => utility [patent_app_number] => 15/005178 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/005178
Method of filling probe indentations in contact pads Jan 24, 2016 Issued
Array ( [id] => 11286475 [patent_doc_number] => 09502334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Method of making a semiconductor device package with dummy gate' [patent_app_type] => utility [patent_app_number] => 14/996979 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14996979 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/996979
Method of making a semiconductor device package with dummy gate Jan 14, 2016 Issued
Array ( [id] => 11539587 [patent_doc_number] => 09614004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Diode/superionic conductor/polymer memory structure' [patent_app_type] => utility [patent_app_number] => 14/965660 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 3423 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/965660
Diode/superionic conductor/polymer memory structure Dec 9, 2015 Issued
Array ( [id] => 10732915 [patent_doc_number] => 20160079065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'LASER ANNEALING DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/944047 [patent_app_country] => US [patent_app_date] => 2015-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4505 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14944047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/944047
Laser annealing device including tunable mask and method of using the same Nov 16, 2015 Issued
Array ( [id] => 11227686 [patent_doc_number] => 09455413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Image pickup device and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 14/942715 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 6845 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942715 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942715
Image pickup device and electronic apparatus Nov 15, 2015 Issued
Array ( [id] => 11214952 [patent_doc_number] => 09443994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Shielded electrical contact and doping through a passivating dielectric layer in a high-efficiency crystalline solar cell, including structure and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 14/885098 [patent_app_country] => US [patent_app_date] => 2015-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 5993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14885098 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/885098
Shielded electrical contact and doping through a passivating dielectric layer in a high-efficiency crystalline solar cell, including structure and methods of manufacture Oct 15, 2015 Issued
Array ( [id] => 10757650 [patent_doc_number] => 20160103802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'METHOD AND SYSTEM FOR FACILITATING ELECTRONIC COMMUNICATION BETWEEN THE PUBLIC AND A PUBLIC PERSONALITY OR REPRESENTATIVE' [patent_app_type] => utility [patent_app_number] => 14/847155 [patent_app_country] => US [patent_app_date] => 2015-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10364 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14847155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/847155
METHOD AND SYSTEM FOR FACILITATING ELECTRONIC COMMUNICATION BETWEEN THE PUBLIC AND A PUBLIC PERSONALITY OR REPRESENTATIVE Sep 7, 2015 Abandoned
Array ( [id] => 11738580 [patent_doc_number] => 09703157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Display device' [patent_app_type] => utility [patent_app_number] => 14/837599 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 42 [patent_no_of_words] => 23314 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837599 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837599
Display device Aug 26, 2015 Issued
Array ( [id] => 10472222 [patent_doc_number] => 20150357238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'METHOD OF MAKING INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/831163 [patent_app_country] => US [patent_app_date] => 2015-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6112 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831163 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831163
Method of making integrated circuit Aug 19, 2015 Issued
Array ( [id] => 10472232 [patent_doc_number] => 20150357248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES' [patent_app_type] => utility [patent_app_number] => 14/828281 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 19572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828281 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828281
METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES Aug 16, 2015 Abandoned
Array ( [id] => 10452480 [patent_doc_number] => 20150337494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'ROLLER DEVICE USING SUCTION ROLLER, AND PRODUCTION METHOD FOR MEMBER HAVING UNEVEN STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/815477 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815477 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815477
ROLLER DEVICE USING SUCTION ROLLER, AND PRODUCTION METHOD FOR MEMBER HAVING UNEVEN STRUCTURE Jul 30, 2015 Abandoned
Array ( [id] => 10447991 [patent_doc_number] => 20150333006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/805570 [patent_app_country] => US [patent_app_date] => 2015-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10303 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14805570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/805570
Semiconductor device having Ti- and N-containing layer, and manufacturing method of same Jul 21, 2015 Issued
Array ( [id] => 10817424 [patent_doc_number] => 20160163586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A VIA STRUCTURE AND AN INTERCONNECTION STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/802086 [patent_app_country] => US [patent_app_date] => 2015-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/802086
Methods of fabricating a semiconductor device having a via structure and an interconnection structure Jul 16, 2015 Issued
Array ( [id] => 10433237 [patent_doc_number] => 20150318249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'SEMICONDUCTOR CHIP HAVING DIFFERENT CONDUCTIVE PAD WIDTHS AND METHOD OF MAKING LAYOUT FOR SAME' [patent_app_type] => utility [patent_app_number] => 14/800955 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800955
Semiconductor chip having different conductive pad widths and method of making layout for same Jul 15, 2015 Issued
Array ( [id] => 12202479 [patent_doc_number] => 09905551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Method of manufacturing wafer level packaging including through encapsulation vias' [patent_app_type] => utility [patent_app_number] => 14/799875 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 67 [patent_no_of_words] => 12817 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/799875
Method of manufacturing wafer level packaging including through encapsulation vias Jul 14, 2015 Issued
Array ( [id] => 11187491 [patent_doc_number] => 09418900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Silicon germanium and silicon fins on oxide from bulk wafer' [patent_app_type] => utility [patent_app_number] => 14/800290 [patent_app_country] => US [patent_app_date] => 2015-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14800290 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/800290
Silicon germanium and silicon fins on oxide from bulk wafer Jul 14, 2015 Issued
Array ( [id] => 11397894 [patent_doc_number] => 20170018432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/797478 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1706 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14797478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/797478
Manufacturing method of semiconductor structure including planarizing a polysilicon layer over an array area and a periphery area Jul 12, 2015 Issued
Array ( [id] => 11796962 [patent_doc_number] => 09406815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Adding decoupling function for TAP cells' [patent_app_type] => utility [patent_app_number] => 14/797614 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14797614 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/797614
Adding decoupling function for TAP cells Jul 12, 2015 Issued
Array ( [id] => 12195558 [patent_doc_number] => 09899291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Method for protecting layer by forming hydrocarbon-based extremely thin film' [patent_app_type] => utility [patent_app_number] => 14/798136 [patent_app_country] => US [patent_app_date] => 2015-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 10428 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14798136 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/798136
Method for protecting layer by forming hydrocarbon-based extremely thin film Jul 12, 2015 Issued
Menu