
John P. Dulka
Examiner (ID: 18278, Phone: (571)270-7398 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2817, 2895 |
| Total Applications | 1000 |
| Issued Applications | 819 |
| Pending Applications | 77 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11207844
[patent_doc_number] => 09437475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-09-06
[patent_title] => 'Method for fabricating microelectronic devices with isolation trenches partially formed under active regions'
[patent_app_type] => utility
[patent_app_number] => 14/441354
[patent_app_country] => US
[patent_app_date] => 2012-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 46
[patent_no_of_words] => 8217
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14441354
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/441354 | Method for fabricating microelectronic devices with isolation trenches partially formed under active regions | Nov 7, 2012 | Issued |
Array
(
[id] => 9552845
[patent_doc_number] => 08759896
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Non-volatile semiconductor memory using charge-accumulation insulating film'
[patent_app_type] => utility
[patent_app_number] => 13/665209
[patent_app_country] => US
[patent_app_date] => 2012-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 9189
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13665209
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/665209 | Non-volatile semiconductor memory using charge-accumulation insulating film | Oct 30, 2012 | Issued |
Array
(
[id] => 9367414
[patent_doc_number] => 20140077287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'BREAKDOWN VOLTAGE BLOCKING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/622997
[patent_app_country] => US
[patent_app_date] => 2012-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 17232
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622997
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/622997 | Breakdown voltage blocking device | Sep 18, 2012 | Issued |
Array
(
[id] => 10590545
[patent_doc_number] => 09312166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-12
[patent_title] => 'Method for manufacturing composite wafers'
[patent_app_type] => utility
[patent_app_number] => 14/343515
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3998
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14343515
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/343515 | Method for manufacturing composite wafers | Sep 13, 2012 | Issued |
Array
(
[id] => 8606697
[patent_doc_number] => 20130012009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'METHOD FOR SELF ALIGNED METAL GATE CMOS'
[patent_app_type] => utility
[patent_app_number] => 13/617528
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2549
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13617528
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/617528 | METHOD FOR SELF ALIGNED METAL GATE CMOS | Sep 13, 2012 | Abandoned |
Array
(
[id] => 10010452
[patent_doc_number] => 09053977
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-09
[patent_title] => 'Nonvolatile memory device with vertical semiconductor pattern between vertical source lines'
[patent_app_type] => utility
[patent_app_number] => 13/610781
[patent_app_country] => US
[patent_app_date] => 2012-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 23
[patent_no_of_words] => 9150
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610781
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/610781 | Nonvolatile memory device with vertical semiconductor pattern between vertical source lines | Sep 10, 2012 | Issued |
Array
(
[id] => 9951717
[patent_doc_number] => 09000510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-07
[patent_title] => 'Nonvolatile memory device with upper source plane and buried bit line'
[patent_app_type] => utility
[patent_app_number] => 13/608652
[patent_app_country] => US
[patent_app_date] => 2012-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 16
[patent_no_of_words] => 4191
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13608652
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/608652 | Nonvolatile memory device with upper source plane and buried bit line | Sep 9, 2012 | Issued |
Array
(
[id] => 8891735
[patent_doc_number] => 20130164919
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-27
[patent_title] => 'METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING GATE INSULATING LAYERS'
[patent_app_type] => utility
[patent_app_number] => 13/605463
[patent_app_country] => US
[patent_app_date] => 2012-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 41
[patent_no_of_words] => 18030
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13605463
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/605463 | Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same | Sep 5, 2012 | Issued |
Array
(
[id] => 10897968
[patent_doc_number] => 08921182
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-30
[patent_title] => 'Method for fabricating 3D nonvolatile memory device with vertical channel hole'
[patent_app_type] => utility
[patent_app_number] => 13/604436
[patent_app_country] => US
[patent_app_date] => 2012-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3559
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604436
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/604436 | Method for fabricating 3D nonvolatile memory device with vertical channel hole | Sep 4, 2012 | Issued |
Array
(
[id] => 9339034
[patent_doc_number] => 20140065816
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-06
[patent_title] => 'DIELECTRIC FORMATION'
[patent_app_type] => utility
[patent_app_number] => 13/600504
[patent_app_country] => US
[patent_app_date] => 2012-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5487
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600504
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/600504 | DIELECTRIC FORMATION | Aug 30, 2012 | Abandoned |
Array
(
[id] => 10145248
[patent_doc_number] => 09178064
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-11-03
[patent_title] => 'Method for manufacturing fin semiconductor device using dual masking layers'
[patent_app_type] => utility
[patent_app_number] => 13/596422
[patent_app_country] => US
[patent_app_date] => 2012-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 19
[patent_no_of_words] => 5211
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13596422
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/596422 | Method for manufacturing fin semiconductor device using dual masking layers | Aug 27, 2012 | Issued |
Array
(
[id] => 9988608
[patent_doc_number] => 09033802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-19
[patent_title] => 'Wagering game system having bonus game configurations'
[patent_app_type] => utility
[patent_app_number] => 13/586387
[patent_app_country] => US
[patent_app_date] => 2012-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 13559
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586387
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/586387 | Wagering game system having bonus game configurations | Aug 14, 2012 | Issued |
Array
(
[id] => 8486993
[patent_doc_number] => 20120286400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'Semiconductor Device with Optical Sensor and Method of Forming Interconnect Structure on Front and Backside of the Device'
[patent_app_type] => utility
[patent_app_number] => 13/555353
[patent_app_country] => US
[patent_app_date] => 2012-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4959
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13555353
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/555353 | Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device | Jul 22, 2012 | Issued |
Array
(
[id] => 9661120
[patent_doc_number] => 08808089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Projection of interactive game environment'
[patent_app_type] => utility
[patent_app_number] => 13/547626
[patent_app_country] => US
[patent_app_date] => 2012-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 7433
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547626
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/547626 | Projection of interactive game environment | Jul 11, 2012 | Issued |
Array
(
[id] => 8450856
[patent_doc_number] => 20120261802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-18
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/529574
[patent_app_country] => US
[patent_app_date] => 2012-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12546
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13529574
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/529574 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Jun 20, 2012 | Abandoned |
Array
(
[id] => 8426721
[patent_doc_number] => 20120248597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-04
[patent_title] => 'SEMICONDUCTOR DEVICE WITH STOP LAYERS AND FABRICATION METHOD USING CERIA SLURRY'
[patent_app_type] => utility
[patent_app_number] => 13/523568
[patent_app_country] => US
[patent_app_date] => 2012-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9357
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13523568
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/523568 | Semiconductor device with stop layers and fabrication method using ceria slurry | Jun 13, 2012 | Issued |
Array
(
[id] => 8368261
[patent_doc_number] => 20120217651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-30
[patent_title] => 'THROUGH SUBSTRATE VIAS'
[patent_app_type] => utility
[patent_app_number] => 13/468609
[patent_app_country] => US
[patent_app_date] => 2012-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6335
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13468609
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/468609 | Through substrate vias | May 9, 2012 | Issued |
Array
(
[id] => 8344735
[patent_doc_number] => 20120205668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-16
[patent_title] => 'SWITCHING SEMICONDUCTOR DEVICES AND FABRICATION PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/454335
[patent_app_country] => US
[patent_app_date] => 2012-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5269
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454335
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/454335 | SWITCHING SEMICONDUCTOR DEVICES AND FABRICATION PROCESS | Apr 23, 2012 | Abandoned |
Array
(
[id] => 8310448
[patent_doc_number] => 20120187476
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-26
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/438058
[patent_app_country] => US
[patent_app_date] => 2012-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4875
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438058
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/438058 | Trench MOS transistor and method of manufacturing the same | Apr 2, 2012 | Issued |
Array
(
[id] => 8237409
[patent_doc_number] => 20120146144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-14
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/402212
[patent_app_country] => US
[patent_app_date] => 2012-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 15239
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402212
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/402212 | Semiconductor device including semiconductor layer over insulating layer and manufacturing method thereof | Feb 21, 2012 | Issued |