
John P. Dulka
Examiner (ID: 19239, Phone: (571)270-7398 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2895, 2811, 2817 |
| Total Applications | 1057 |
| Issued Applications | 848 |
| Pending Applications | 91 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18815021
[patent_doc_number] => 20230389359
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/447332
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8457
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447332
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447332 | Display device with peripheral wiring surounding sensor area | Aug 9, 2023 | Issued |
Array
(
[id] => 18977309
[patent_doc_number] => 20240057401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/229392
[patent_app_country] => US
[patent_app_date] => 2023-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17939
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229392
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/229392 | DISPLAY APPARATUS | Aug 1, 2023 | Pending |
Array
(
[id] => 18906192
[patent_doc_number] => 20240021677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => PACKAGED STRUCTURES FOR LATERAL HIGH VOLTAGE GALLIUM NITRIDE DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/363873
[patent_app_country] => US
[patent_app_date] => 2023-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3586
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363873
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/363873 | PACKAGED STRUCTURES FOR LATERAL HIGH VOLTAGE GALLIUM NITRIDE DEVICES | Aug 1, 2023 | Pending |
Array
(
[id] => 18812940
[patent_doc_number] => 20230387277
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE
[patent_app_type] => utility
[patent_app_number] => 18/361758
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10225
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361758
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361758 | Gated metal-insulator-semiconductor (MIS) tunnel diode having negative transconductance | Jul 27, 2023 | Issued |
Array
(
[id] => 18812681
[patent_doc_number] => 20230387018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE
[patent_app_type] => utility
[patent_app_number] => 18/359383
[patent_app_country] => US
[patent_app_date] => 2023-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4577
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359383
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/359383 | Graphene barrier layer for reduced contact resistance | Jul 25, 2023 | Issued |
Array
(
[id] => 19191694
[patent_doc_number] => 20240170607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/357433
[patent_app_country] => US
[patent_app_date] => 2023-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4076
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357433
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/357433 | SEMICONDUCTOR STRUCTURE | Jul 23, 2023 | Pending |
Array
(
[id] => 18757775
[patent_doc_number] => 20230361238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => METHOD FOR MANUFACTURING MONOCRYSTALLINE SILICON WAFER CONTAINING ARCED SIDE, METHOD FOR MANUFACTURING MONOCRYSTALLINE SILICON CELL, AND PHOTOVOLTAIC MODULE
[patent_app_type] => utility
[patent_app_number] => 18/222377
[patent_app_country] => US
[patent_app_date] => 2023-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4540
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222377
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/222377 | Method for manufacturing monocrystalline silicon wafer containing arced side, method for manufacturing monocrystalline silicon cell, and photovoltaic module | Jul 13, 2023 | Issued |
Array
(
[id] => 20119560
[patent_doc_number] => 12369298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Semiconductor device with etched landing pad surface and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/218212
[patent_app_country] => US
[patent_app_date] => 2023-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 5477
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218212
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/218212 | Semiconductor device with etched landing pad surface and manufacturing method thereof | Jul 4, 2023 | Issued |
Array
(
[id] => 19690303
[patent_doc_number] => 20250008848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => LOW DRIFT PHASE CHANGE MATERIAL COMPOSITE MATRIX
[patent_app_type] => utility
[patent_app_number] => 18/344194
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8799
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344194
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344194 | LOW DRIFT PHASE CHANGE MATERIAL COMPOSITE MATRIX | Jun 28, 2023 | Pending |
Array
(
[id] => 19507973
[patent_doc_number] => 12119404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-15
[patent_title] => Gate all around structure with additional silicon layer and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 18/344057
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 56
[patent_figures_cnt] => 56
[patent_no_of_words] => 10056
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344057
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344057 | Gate all around structure with additional silicon layer and method for forming the same | Jun 28, 2023 | Issued |
Array
(
[id] => 18729383
[patent_doc_number] => 20230343679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A CONNECTIVE PATH
[patent_app_type] => utility
[patent_app_number] => 18/215631
[patent_app_country] => US
[patent_app_date] => 2023-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20402
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215631
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/215631 | 3D semiconductor device and structure with metal layers and a connective path | Jun 27, 2023 | Issued |
Array
(
[id] => 19646430
[patent_doc_number] => 20240420950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => DENSIFIED SEAM-FREE SILICON-CONTAINING MATERIAL GAP FILL PROCESSES
[patent_app_type] => utility
[patent_app_number] => 18/209732
[patent_app_country] => US
[patent_app_date] => 2023-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8665
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209732
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/209732 | DENSIFIED SEAM-FREE SILICON-CONTAINING MATERIAL GAP FILL PROCESSES | Jun 13, 2023 | Pending |
Array
(
[id] => 18680089
[patent_doc_number] => 20230317747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => CAMERA MODULE HAVING CIRCUIT BOARD, PHOTOSENSITIVE ELEMENT, OPTICAL LENS, AND FILTER ELEMENT
[patent_app_type] => utility
[patent_app_number] => 18/207357
[patent_app_country] => US
[patent_app_date] => 2023-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 58125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207357
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/207357 | Circuit board assembly with photosensitive element mounted to back side of circuit board | Jun 7, 2023 | Issued |
Array
(
[id] => 18776406
[patent_doc_number] => 20230371244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => MEMORY DEVICE HAVING VERTICAL TRANSISTORS AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/197505
[patent_app_country] => US
[patent_app_date] => 2023-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15394
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197505
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/197505 | Memory device having an array of vertical transistors with associated lines and method for forming the same | May 14, 2023 | Issued |
Array
(
[id] => 19690244
[patent_doc_number] => 20250008789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/275025
[patent_app_country] => US
[patent_app_date] => 2023-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6831
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18275025
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/275025 | DISPLAY PANEL AND DISPLAY DEVICE | May 11, 2023 | Pending |
Array
(
[id] => 18884895
[patent_doc_number] => 20240008264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => SEMICONDUCTOR DEVICE WITH VANADIUM-CONTAINING SPACERS AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/195512
[patent_app_country] => US
[patent_app_date] => 2023-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9093
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195512
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/195512 | Semiconductor device with vanadium-containing spacers and method for fabricating the same | May 9, 2023 | Issued |
Array
(
[id] => 19575213
[patent_doc_number] => 20240379505
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-14
[patent_title] => Bond Films for Reduced Thermal Resistance and Methods Forming the Same
[patent_app_type] => utility
[patent_app_number] => 18/314356
[patent_app_country] => US
[patent_app_date] => 2023-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7012
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314356
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/314356 | Bond Films for Reduced Thermal Resistance and Methods Forming the Same | May 8, 2023 | Pending |
Array
(
[id] => 19720313
[patent_doc_number] => 12205856
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Semiconductor structure including interconnection to probe pad with probe mark
[patent_app_type] => utility
[patent_app_number] => 18/314126
[patent_app_country] => US
[patent_app_date] => 2023-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 10194
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314126
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/314126 | Semiconductor structure including interconnection to probe pad with probe mark | May 7, 2023 | Issued |
Array
(
[id] => 19148579
[patent_doc_number] => 20240147697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/308376
[patent_app_country] => US
[patent_app_date] => 2023-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308376
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/308376 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | Apr 26, 2023 | Pending |
Array
(
[id] => 18570472
[patent_doc_number] => 20230260809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-17
[patent_title] => LASER LIGHT SOURCE AND A LASER CRYSTALLIZATION APPARATUS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/139414
[patent_app_country] => US
[patent_app_date] => 2023-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9099
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139414
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/139414 | Laser light source and a laser crystallization apparatus including the same | Apr 25, 2023 | Issued |