
John P. Dulka
Examiner (ID: 18278, Phone: (571)270-7398 , Office: P/2895 )
| Most Active Art Unit | 2895 |
| Art Unit(s) | 2817, 2895 |
| Total Applications | 1000 |
| Issued Applications | 819 |
| Pending Applications | 77 |
| Abandoned Applications | 143 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5432212
[patent_doc_number] => 20090166798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-02
[patent_title] => 'DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION'
[patent_app_type] => utility
[patent_app_number] => 11/964337
[patent_app_country] => US
[patent_app_date] => 2007-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4315
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20090166798.pdf
[firstpage_image] =>[orig_patent_app_number] => 11964337
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/964337 | DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION | Dec 25, 2007 | Abandoned |
Array
(
[id] => 5419725
[patent_doc_number] => 20090146179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'Planar arrays of photodiodes'
[patent_app_type] => utility
[patent_app_number] => 12/004597
[patent_app_country] => US
[patent_app_date] => 2007-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4948
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20090146179.pdf
[firstpage_image] =>[orig_patent_app_number] => 12004597
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/004597 | Planar arrays of photodiodes | Dec 20, 2007 | Abandoned |
Array
(
[id] => 4859360
[patent_doc_number] => 20080268210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'MANUFACTURING METHOD OF ELECTRONIC COMPONENT'
[patent_app_type] => utility
[patent_app_number] => 11/960200
[patent_app_country] => US
[patent_app_date] => 2007-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5625
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0268/20080268210.pdf
[firstpage_image] =>[orig_patent_app_number] => 11960200
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/960200 | MANUFACTURING METHOD OF ELECTRONIC COMPONENT | Dec 18, 2007 | Abandoned |
Array
(
[id] => 4843199
[patent_doc_number] => 20080179607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-31
[patent_title] => 'Non-polar and semi-polar light emitting devices'
[patent_app_type] => utility
[patent_app_number] => 12/001227
[patent_app_country] => US
[patent_app_date] => 2007-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 7873
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20080179607.pdf
[firstpage_image] =>[orig_patent_app_number] => 12001227
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/001227 | Non-polar and semi-polar light emitting devices | Dec 10, 2007 | Issued |
Array
(
[id] => 8807680
[patent_doc_number] => 08445332
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-21
[patent_title] => 'Single crystal silicon rod fabrication methods and a single crystal silicon rod structure'
[patent_app_type] => utility
[patent_app_number] => 11/976009
[patent_app_country] => US
[patent_app_date] => 2007-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 5732
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11976009
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/976009 | Single crystal silicon rod fabrication methods and a single crystal silicon rod structure | Oct 18, 2007 | Issued |
Array
(
[id] => 5282335
[patent_doc_number] => 20090096009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE'
[patent_app_type] => utility
[patent_app_number] => 11/872998
[patent_app_country] => US
[patent_app_date] => 2007-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2095
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20090096009.pdf
[firstpage_image] =>[orig_patent_app_number] => 11872998
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/872998 | NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE | Oct 15, 2007 | Abandoned |
Array
(
[id] => 5524731
[patent_doc_number] => 20090194807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-06
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/870839
[patent_app_country] => US
[patent_app_date] => 2007-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3769
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20090194807.pdf
[firstpage_image] =>[orig_patent_app_number] => 11870839
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/870839 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME | Oct 10, 2007 | Abandoned |
Array
(
[id] => 4745813
[patent_doc_number] => 20080090415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-17
[patent_title] => 'Substrate processing apparatus, method of manufacturing a semiconductor device, and method of forming a thin film on metal surface'
[patent_app_type] => utility
[patent_app_number] => 11/907270
[patent_app_country] => US
[patent_app_date] => 2007-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8914
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20080090415.pdf
[firstpage_image] =>[orig_patent_app_number] => 11907270
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/907270 | Substrate processing apparatus, method of manufacturing a semiconductor device, and method of forming a thin film on metal surface | Oct 9, 2007 | Issued |
Array
(
[id] => 6609481
[patent_doc_number] => 20100099254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'SEMICONDUCTOR MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, STORAGE MEDIUM AND COMPUTER PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/443983
[patent_app_country] => US
[patent_app_date] => 2007-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6827
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0099/20100099254.pdf
[firstpage_image] =>[orig_patent_app_number] => 12443983
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/443983 | SEMICONDUCTOR MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, STORAGE MEDIUM AND COMPUTER PROGRAM | Sep 30, 2007 | Abandoned |
Array
(
[id] => 4695496
[patent_doc_number] => 20080217680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-11
[patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY USING CHARGE-ACCUMULATION INSULATING FILM'
[patent_app_type] => utility
[patent_app_number] => 11/854090
[patent_app_country] => US
[patent_app_date] => 2007-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9174
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0217/20080217680.pdf
[firstpage_image] =>[orig_patent_app_number] => 11854090
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/854090 | Non-volatile semiconductor memory using charge-accumulation insulating film | Sep 11, 2007 | Issued |
Array
(
[id] => 7730767
[patent_doc_number] => 08101976
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-24
[patent_title] => 'Device selection circuitry constructed with nanotube ribbon technology'
[patent_app_type] => utility
[patent_app_number] => 11/853550
[patent_app_country] => US
[patent_app_date] => 2007-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 6426
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/101/08101976.pdf
[firstpage_image] =>[orig_patent_app_number] => 11853550
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/853550 | Device selection circuitry constructed with nanotube ribbon technology | Sep 10, 2007 | Issued |
Array
(
[id] => 4816868
[patent_doc_number] => 20080224127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-18
[patent_title] => 'Gate dielectric structures, organic semiconductors, thin film transistors and related methods'
[patent_app_type] => utility
[patent_app_number] => 11/895000
[patent_app_country] => US
[patent_app_date] => 2007-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 13698
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20080224127.pdf
[firstpage_image] =>[orig_patent_app_number] => 11895000
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/895000 | Gate dielectric structures, organic semiconductors, thin film transistors and related methods | Aug 21, 2007 | Abandoned |
Array
(
[id] => 4762809
[patent_doc_number] => 20080174018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-24
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/889390
[patent_app_country] => US
[patent_app_date] => 2007-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10881
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20080174018.pdf
[firstpage_image] =>[orig_patent_app_number] => 11889390
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/889390 | Semiconductor device and method for fabricating the same | Aug 12, 2007 | Abandoned |
Array
(
[id] => 4458746
[patent_doc_number] => 07879263
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Method and solution to grow charge-transfer complex salts'
[patent_app_type] => utility
[patent_app_number] => 11/880687
[patent_app_country] => US
[patent_app_date] => 2007-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 9356
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/879/07879263.pdf
[firstpage_image] =>[orig_patent_app_number] => 11880687
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/880687 | Method and solution to grow charge-transfer complex salts | Jul 23, 2007 | Issued |
Array
(
[id] => 4654978
[patent_doc_number] => 20080023838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-31
[patent_title] => 'Manufacturing method of semiconductor device and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/878020
[patent_app_country] => US
[patent_app_date] => 2007-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10304
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20080023838.pdf
[firstpage_image] =>[orig_patent_app_number] => 11878020
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/878020 | Semiconductor device having oxidized Ti- and N-containing layer, and manufacturing of the same | Jul 19, 2007 | Issued |
Array
(
[id] => 4685636
[patent_doc_number] => 20080029817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-07
[patent_title] => 'Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured'
[patent_app_type] => utility
[patent_app_number] => 11/879738
[patent_app_country] => US
[patent_app_date] => 2007-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4129
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0029/20080029817.pdf
[firstpage_image] =>[orig_patent_app_number] => 11879738
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/879738 | Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured | Jul 16, 2007 | Issued |
Array
(
[id] => 5407411
[patent_doc_number] => 20090121309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-14
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/767369
[patent_app_country] => US
[patent_app_date] => 2007-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3051
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20090121309.pdf
[firstpage_image] =>[orig_patent_app_number] => 11767369
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/767369 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Jun 21, 2007 | Abandoned |
Array
(
[id] => 9441397
[patent_doc_number] => 08710510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-29
[patent_title] => 'High power insulated gate bipolar transistors'
[patent_app_type] => utility
[patent_app_number] => 11/764492
[patent_app_country] => US
[patent_app_date] => 2007-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 6737
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11764492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/764492 | High power insulated gate bipolar transistors | Jun 17, 2007 | Issued |
Array
(
[id] => 5558599
[patent_doc_number] => 20090270176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-29
[patent_title] => 'PERIPHERAL UPDATE PERIPHERAL IN A WAGERING GAME SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/304229
[patent_app_country] => US
[patent_app_date] => 2007-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10690
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0270/20090270176.pdf
[firstpage_image] =>[orig_patent_app_number] => 12304229
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/304229 | Peripheral update peripheral in a wagering game system | Jun 12, 2007 | Issued |
Array
(
[id] => 63658
[patent_doc_number] => 07763958
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-07-27
[patent_title] => 'Leadframe panel for power packages'
[patent_app_type] => utility
[patent_app_number] => 11/754070
[patent_app_country] => US
[patent_app_date] => 2007-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4588
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/763/07763958.pdf
[firstpage_image] =>[orig_patent_app_number] => 11754070
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/754070 | Leadframe panel for power packages | May 24, 2007 | Issued |