Search

John P. Dulka

Examiner (ID: 11799)

Most Active Art Unit
2895
Art Unit(s)
2811, 2895, 2817
Total Applications
1037
Issued Applications
839
Pending Applications
81
Abandoned Applications
143

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18423935 [patent_doc_number] => 20230178399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SYSTEMS AND METHODS FOR SYSTEMATIC PHYSICAL FAILURE ANALYSIS (PFA) FAULT LOCALIZATION [patent_app_type] => utility [patent_app_number] => 18/163821 [patent_app_country] => US [patent_app_date] => 2023-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18163821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/163821
Systems and methods for systematic physical failure analysis (PFA) fault localization Feb 1, 2023 Issued
Array ( [id] => 18408897 [patent_doc_number] => 20230170250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH OXIDE BONDING [patent_app_type] => utility [patent_app_number] => 18/102710 [patent_app_country] => US [patent_app_date] => 2023-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18102710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/102710
Multilevel semiconductor device and structure with oxide bonding Jan 27, 2023 Issued
Array ( [id] => 20705875 [patent_doc_number] => 12628607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Optical heating device with angled light holding substrate and method of heating treatment thereof [patent_app_type] => utility [patent_app_number] => 18/159590 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6472 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/159590
Optical heating device with angled light holding substrate and method of heating treatment thereof Jan 24, 2023 Issued
Array ( [id] => 18379775 [patent_doc_number] => 20230154864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => Molded Laser Package with Electromagnetic Interference Shield and Method of Making [patent_app_type] => utility [patent_app_number] => 18/155878 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18155878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/155878
Molded laser package with electromagnetic interference shield and method of making Jan 17, 2023 Issued
Array ( [id] => 18886121 [patent_doc_number] => 11864877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Health monitoring device including pinned photodiode [patent_app_type] => utility [patent_app_number] => 18/149690 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11587 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149690
Health monitoring device including pinned photodiode Jan 3, 2023 Issued
Array ( [id] => 19285951 [patent_doc_number] => 20240222428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEEDED GROWTH FOR 2D NANORIBBON TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/091206 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091206 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091206
SEEDED GROWTH FOR 2D NANORIBBON TRANSISTORS Dec 28, 2022 Pending
Array ( [id] => 19269531 [patent_doc_number] => 20240213235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ARCHITECTURES FOR BACKSIDE POWER DELIVERY WITH STACKED INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 18/089459 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089459
ARCHITECTURES FOR BACKSIDE POWER DELIVERY WITH STACKED INTEGRATED CIRCUIT DEVICES Dec 26, 2022 Pending
Array ( [id] => 19153791 [patent_doc_number] => 11978714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-07 [patent_title] => Encapsulated package including device dies connected via interconnect die [patent_app_type] => utility [patent_app_number] => 18/068064 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 6939 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/068064
Encapsulated package including device dies connected via interconnect die Dec 18, 2022 Issued
Array ( [id] => 19252800 [patent_doc_number] => 20240203797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => THREE-DIMENSIONAL MULTIPLE LOCATION COMPRESSING BONDED ARM-POISEDON 4 AND POISEDON 5 ADVANCED INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/081207 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18081207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/081207
3D multiple location compressing bonded arm for advanced integration Dec 13, 2022 Issued
Array ( [id] => 18311836 [patent_doc_number] => 20230115736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => INTERACTIVE ENVIRONMENT WITH VIRTUAL ENVIRONMENT SPACE SCANNING [patent_app_type] => utility [patent_app_number] => 18/080678 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080678
INTERACTIVE ENVIRONMENT WITH VIRTUAL ENVIRONMENT SPACE SCANNING Dec 12, 2022 Abandoned
Array ( [id] => 18266545 [patent_doc_number] => 20230087787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A CONNECTIVE PATH [patent_app_type] => utility [patent_app_number] => 18/070422 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070422
3D semiconductor device and structure with metal layers and a connective path Nov 27, 2022 Issued
Array ( [id] => 19176392 [patent_doc_number] => 20240162366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => INVERSION LAYER APD [patent_app_type] => utility [patent_app_number] => 18/054871 [patent_app_country] => US [patent_app_date] => 2022-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054871 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054871
Inversion layer avalanche photodiode with vertical electric field Nov 10, 2022 Issued
Array ( [id] => 18704692 [patent_doc_number] => 11791209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/971807 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 48 [patent_no_of_words] => 11410 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/971807
Method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device Oct 23, 2022 Issued
Array ( [id] => 19086150 [patent_doc_number] => 20240112951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH NIOBIUM BARRIER MATERIALS [patent_app_type] => utility [patent_app_number] => 17/957721 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957721 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/957721
INTEGRATED CIRCUIT INTERCONNECT STRUCTURES WITH NIOBIUM BARRIER MATERIALS Sep 29, 2022 Pending
Array ( [id] => 18112941 [patent_doc_number] => 20230005821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND A CONNECTIVE PATH [patent_app_type] => utility [patent_app_number] => 17/941891 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941891
3D semiconductor device and structure with metal layers and a connective path Sep 8, 2022 Issued
Array ( [id] => 20376880 [patent_doc_number] => 12484338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Chip fabrication process for improving LED chip light extraction efficiency with isolation groove and LED chip thereof [patent_app_type] => utility [patent_app_number] => 17/927504 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1233 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17927504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/927504
Chip fabrication process for improving LED chip light extraction efficiency with isolation groove and LED chip thereof Sep 7, 2022 Issued
Array ( [id] => 18696330 [patent_doc_number] => 20230326767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => WAFER SHAPE CONTROL FOR W2W BONDING [patent_app_type] => utility [patent_app_number] => 17/885097 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885097
Wafer shape control for W2W bonding Aug 9, 2022 Issued
Array ( [id] => 18196923 [patent_doc_number] => 20230050442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING SEMICONDUCTOR WAFERS USING FRONT-END PROCESSED WAFER GLOBAL GEOMETRY METRICS [patent_app_type] => utility [patent_app_number] => 17/818123 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818123
Semiconductor wafers using front-end processed wafer global geometry metrics Aug 7, 2022 Issued
Array ( [id] => 19926241 [patent_doc_number] => 12300534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Method of forming protective layer utilized in silicon remove process [patent_app_type] => utility [patent_app_number] => 17/880685 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880685
Method of forming protective layer utilized in silicon remove process Aug 3, 2022 Issued
Array ( [id] => 18579126 [patent_doc_number] => 11735666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Gate all around structure with additional silicon layer and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/814881 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 9527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814881
Gate all around structure with additional silicon layer and method for forming the same Jul 25, 2022 Issued
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