Search

John P. Lacyk

Examiner (ID: 6851, Phone: (571)272-4728 , Office: P/3735 )

Most Active Art Unit
3735
Art Unit(s)
8300, 3736, 3791, 3311, 3305, 2899, 3735
Total Applications
2989
Issued Applications
2231
Pending Applications
277
Abandoned Applications
491

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19900280 [patent_doc_number] => 12278218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/923340 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6979 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18923340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/923340
Semiconductor device Oct 21, 2024 Issued
Array ( [id] => 19843184 [patent_doc_number] => 12255591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Temperature compensation bias circuit and power amplifier [patent_app_type] => utility [patent_app_number] => 18/806715 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4637 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806715 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/806715
Temperature compensation bias circuit and power amplifier Aug 15, 2024 Issued
Array ( [id] => 20381861 [patent_doc_number] => 20250364354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => PACKAGE STRUCTURE INCLUDING HEAT SINK STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/741149 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741149
PACKAGE STRUCTURE INCLUDING HEAT SINK STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Jun 11, 2024 Pending
Array ( [id] => 19484160 [patent_doc_number] => 20240332202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PACKAGE STRUCTURE WITH BRIDGE DIE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/735194 [patent_app_country] => US [patent_app_date] => 2024-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735194 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735194
Package structure with bridge die and method of forming the package structure Jun 5, 2024 Issued
Array ( [id] => 19467991 [patent_doc_number] => 20240321661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PACKAGES WITH MULTIPLE ENCAPSULATED SUBSTRATE BLOCKS [patent_app_type] => utility [patent_app_number] => 18/679091 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679091
PACKAGES WITH MULTIPLE ENCAPSULATED SUBSTRATE BLOCKS May 29, 2024 Pending
Array ( [id] => 20111539 [patent_doc_number] => 12362275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Method of fabricating package structure including a plurality of antenna patterns [patent_app_type] => utility [patent_app_number] => 18/672001 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 1140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672001
Method of fabricating package structure including a plurality of antenna patterns May 22, 2024 Issued
Array ( [id] => 19619298 [patent_doc_number] => 20240404978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/671520 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671520
WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD May 21, 2024 Pending
Array ( [id] => 20313534 [patent_doc_number] => 20250331163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 18/665064 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665064
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SAME May 14, 2024 Pending
Array ( [id] => 20612606 [patent_doc_number] => 12588222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Semiconductor package including an integrated circuit die and an inductor or a transformer [patent_app_type] => utility [patent_app_number] => 18/663697 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 51 [patent_no_of_words] => 7601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663697 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663697
Semiconductor package including an integrated circuit die and an inductor or a transformer May 13, 2024 Issued
Array ( [id] => 20404771 [patent_doc_number] => 12494755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Apparatus and method of power management using envelope stacking [patent_app_type] => utility [patent_app_number] => 18/661761 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 7558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661761 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661761
Apparatus and method of power management using envelope stacking May 12, 2024 Issued
Array ( [id] => 19407943 [patent_doc_number] => 20240291454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => POWER RECONFIGURABLE POWER AMPLIFIER [patent_app_type] => utility [patent_app_number] => 18/659409 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/659409
POWER RECONFIGURABLE POWER AMPLIFIER May 8, 2024 Pending
Array ( [id] => 19560194 [patent_doc_number] => 20240371986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => QUANTUM DEVICE INCLUDING MODERATE FLUORIATED GRAPHENE AND METHOD FOR FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 18/654150 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654150
QUANTUM DEVICE INCLUDING MODERATE FLUORIATED GRAPHENE AND METHOD FOR FABRICATING SAME May 2, 2024 Pending
Array ( [id] => 20002524 [patent_doc_number] => 20250140746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/654916 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654916
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF May 2, 2024 Pending
Array ( [id] => 20346022 [patent_doc_number] => 12469757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Package structure including a die having a taper-shaped die connector [patent_app_type] => utility [patent_app_number] => 18/652779 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 103 [patent_no_of_words] => 16562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652779
Package structure including a die having a taper-shaped die connector Apr 30, 2024 Issued
Array ( [id] => 20389339 [patent_doc_number] => 12489074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Package structure having a device inside a molding member and method of forming the package structure [patent_app_type] => utility [patent_app_number] => 18/650143 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 46 [patent_no_of_words] => 4425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650143 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650143
Package structure having a device inside a molding member and method of forming the package structure Apr 29, 2024 Issued
Array ( [id] => 19646617 [patent_doc_number] => 20240421137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CHIP PACKAGE UNIT, CHIP PACKAGE STACK MODULE, AND METHOD OF MANUFACTURING CHIP PACKAGE STACK MODULE [patent_app_type] => utility [patent_app_number] => 18/645411 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645411 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645411
CHIP PACKAGE UNIT, CHIP PACKAGE STACK MODULE, AND METHOD OF MANUFACTURING CHIP PACKAGE STACK MODULE Apr 24, 2024 Pending
Array ( [id] => 19392803 [patent_doc_number] => 20240282673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => METHODS FOR FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 18/643322 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643322
Semiconductor device including a memory stack and a contact structure in a spacer structure Apr 22, 2024 Issued
Menu