Search

John P. Lacyk

Examiner (ID: 7526, Phone: (571)272-4728 , Office: P/3735 )

Most Active Art Unit
3735
Art Unit(s)
3735, 3311, 3736, 3791, 2899, 3305, 8300
Total Applications
2989
Issued Applications
2231
Pending Applications
277
Abandoned Applications
491

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17373731 [patent_doc_number] => 20220028783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => TOP VIA STACK [patent_app_type] => utility [patent_app_number] => 17/496252 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496252
Top via stack Oct 6, 2021 Issued
Array ( [id] => 18528925 [patent_doc_number] => 11715931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-01 [patent_title] => Strained and strain control regions in optical devices [patent_app_type] => utility [patent_app_number] => 17/495378 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 18215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495378
Strained and strain control regions in optical devices Oct 5, 2021 Issued
Array ( [id] => 18840189 [patent_doc_number] => 11848269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Techniques to create power connections from floating nets in standard cells [patent_app_type] => utility [patent_app_number] => 17/493574 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493574
Techniques to create power connections from floating nets in standard cells Oct 3, 2021 Issued
Array ( [id] => 18874734 [patent_doc_number] => 11862557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Selectable monolithic or external scalable die-to-die interconnection system methodology [patent_app_type] => utility [patent_app_number] => 17/483535 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 10857 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483535
Selectable monolithic or external scalable die-to-die interconnection system methodology Sep 22, 2021 Issued
Array ( [id] => 17339381 [patent_doc_number] => 20220005712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Method of Processing Substrate Support [patent_app_type] => utility [patent_app_number] => 17/477079 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477079
Substrate processing apparatus, method of manufacturing semiconductor device and method of processing substrate support Sep 15, 2021 Issued
Array ( [id] => 18254914 [patent_doc_number] => 20230081953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => DECOUPLED INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/447586 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447586
Decoupled interconnect structures Sep 13, 2021 Issued
Array ( [id] => 17359948 [patent_doc_number] => 20220020744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => HIGH PERFORMANCE NANOSHEET FABRICATION METHOD WITH ENHANCED HIGH MOBILITY CHANNEL ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/447506 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447506
High performance nanosheet fabrication method with enhanced high mobility channel elements Sep 12, 2021 Issued
Array ( [id] => 20386730 [patent_doc_number] => 12486448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Perovskite compound-based electroluminescent layer and light emitting device comprising same [patent_app_type] => utility [patent_app_number] => 18/044839 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3375 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18044839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/044839
Perovskite compound-based electroluminescent layer and light emitting device comprising same Sep 9, 2021 Issued
Array ( [id] => 18874786 [patent_doc_number] => 11862609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor die including fuse structure and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/472115 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6250 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472115
Semiconductor die including fuse structure and methods for forming the same Sep 9, 2021 Issued
Array ( [id] => 19796312 [patent_doc_number] => 12237281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Electronic package and implantable medical device including same [patent_app_type] => utility [patent_app_number] => 17/469098 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469098
Electronic package and implantable medical device including same Sep 7, 2021 Issued
Array ( [id] => 17318954 [patent_doc_number] => 20210408004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/469340 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469340
Semiconductor device and method of fabricating the same Sep 7, 2021 Issued
Array ( [id] => 18241870 [patent_doc_number] => 20230074181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => LOW COST EMBEDDED INTEGRATED CIRCUIT DIES [patent_app_type] => utility [patent_app_number] => 17/467666 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467666
Low cost embedded integrated circuit dies Sep 6, 2021 Issued
Array ( [id] => 19370533 [patent_doc_number] => 12062627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/467964 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8343 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467964
Semiconductor device Sep 6, 2021 Issued
Array ( [id] => 18048018 [patent_doc_number] => 11521976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Semiconductor device with bit line contact and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/466102 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466102
Semiconductor device with bit line contact and method for fabricating the same Sep 2, 2021 Issued
Array ( [id] => 19244542 [patent_doc_number] => 12014997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Dummy stacked structures surrounding TSVs and method forming the same [patent_app_type] => utility [patent_app_number] => 17/464903 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 7643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464903
Dummy stacked structures surrounding TSVs and method forming the same Sep 1, 2021 Issued
Array ( [id] => 17448288 [patent_doc_number] => 20220068793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE FORMED ON SOI SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/460998 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460998
Semiconductor device formed on SOI substrate Aug 29, 2021 Issued
Array ( [id] => 19229652 [patent_doc_number] => 12009296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/461924 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4223 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461924
Semiconductor device and manufacturing method thereof Aug 29, 2021 Issued
Array ( [id] => 18464412 [patent_doc_number] => 11688708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Chip structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/460937 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460937
Chip structure and method for forming the same Aug 29, 2021 Issued
Array ( [id] => 18223033 [patent_doc_number] => 20230062027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DIE INCLUDING GUARD RING STRUCTURE AND THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/458687 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458687
Semiconductor die including guard ring structure and three-dimensional device structure including the same Aug 26, 2021 Issued
Array ( [id] => 18230321 [patent_doc_number] => 20230069315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING SUBSTRATE-EMBEDDED INTEGRATED PASSIVE DEVICE AND METHODS FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/446053 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446053
Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same Aug 25, 2021 Issued
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