Search

John P. Sheehan

Examiner (ID: 18126)

Most Active Art Unit
1101
Art Unit(s)
1101, 1308, 3203, 1111, 1311, 1754, 1102, 1742, 1793, 1736
Total Applications
2472
Issued Applications
1968
Pending Applications
52
Abandoned Applications
452

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 658042 [patent_doc_number] => 07105363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Cladded conductor for use in a magnetoelectronics device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/082617 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2847 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105363.pdf [firstpage_image] =>[orig_patent_app_number] => 11082617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/082617
Cladded conductor for use in a magnetoelectronics device and method for fabricating the same Mar 15, 2005 Issued
Array ( [id] => 401189 [patent_doc_number] => 07291553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-06 [patent_title] => 'Method for forming dual damascene with improved etch profiles' [patent_app_type] => utility [patent_app_number] => 11/075777 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3501 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/291/07291553.pdf [firstpage_image] =>[orig_patent_app_number] => 11075777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/075777
Method for forming dual damascene with improved etch profiles Mar 7, 2005 Issued
Array ( [id] => 5785571 [patent_doc_number] => 20060205133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same' [patent_app_type] => utility [patent_app_number] => 11/076497 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4526 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205133.pdf [firstpage_image] =>[orig_patent_app_number] => 11076497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/076497
Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same Mar 7, 2005 Issued
Array ( [id] => 5785724 [patent_doc_number] => 20060205220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Stabilized photoresist structure for etching process' [patent_app_type] => utility [patent_app_number] => 11/076087 [patent_app_country] => US [patent_app_date] => 2005-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4491 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20060205220.pdf [firstpage_image] =>[orig_patent_app_number] => 11076087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/076087
Stabilized photoresist structure for etching process Mar 7, 2005 Issued
Array ( [id] => 363875 [patent_doc_number] => 07482690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Electronic components such as thin array plastic packages and process for fabricating same' [patent_app_type] => utility [patent_app_number] => 11/071737 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 90 [patent_no_of_words] => 6608 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482690.pdf [firstpage_image] =>[orig_patent_app_number] => 11071737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071737
Electronic components such as thin array plastic packages and process for fabricating same Mar 2, 2005 Issued
Array ( [id] => 5683118 [patent_doc_number] => 20060199388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'System and method for manufacturing semiconductor devices using a vacuum chamber' [patent_app_type] => utility [patent_app_number] => 11/069177 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3028 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199388.pdf [firstpage_image] =>[orig_patent_app_number] => 11069177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069177
System and method for manufacturing semiconductor devices using a vacuum chamber Feb 28, 2005 Issued
Array ( [id] => 5705380 [patent_doc_number] => 20060194428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Control of wafer warpage during backend processing' [patent_app_type] => utility [patent_app_number] => 11/068237 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3744 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20060194428.pdf [firstpage_image] =>[orig_patent_app_number] => 11068237 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068237
Control of wafer warpage during backend processing Feb 27, 2005 Issued
Array ( [id] => 907160 [patent_doc_number] => 07332428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Metal interconnect structure and method' [patent_app_type] => utility [patent_app_number] => 11/067877 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5041 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332428.pdf [firstpage_image] =>[orig_patent_app_number] => 11067877 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067877
Metal interconnect structure and method Feb 27, 2005 Issued
Array ( [id] => 810110 [patent_doc_number] => 07416969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Void free solder arrangement for screen printing semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/067597 [patent_app_country] => US [patent_app_date] => 2005-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2458 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/416/07416969.pdf [firstpage_image] =>[orig_patent_app_number] => 11067597 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067597
Void free solder arrangement for screen printing semiconductor wafers Feb 25, 2005 Issued
Array ( [id] => 806681 [patent_doc_number] => 07419915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Laser assisted chemical etching method for release microscale and nanoscale devices' [patent_app_type] => utility [patent_app_number] => 11/061485 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2720 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/419/07419915.pdf [firstpage_image] =>[orig_patent_app_number] => 11061485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061485
Laser assisted chemical etching method for release microscale and nanoscale devices Feb 16, 2005 Issued
Array ( [id] => 620435 [patent_doc_number] => 07141852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Semiconductor device and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/027837 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3181 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141852.pdf [firstpage_image] =>[orig_patent_app_number] => 11027837 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027837
Semiconductor device and fabricating method thereof Dec 28, 2004 Issued
Array ( [id] => 7253824 [patent_doc_number] => 20050142861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of forming an interconnection line in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/020277 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3854 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142861.pdf [firstpage_image] =>[orig_patent_app_number] => 11020277 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020277
Method of forming an interconnection line in a semiconductor device Dec 26, 2004 Issued
Array ( [id] => 453068 [patent_doc_number] => 07247579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Cleaning methods for silicon electrode assembly surface contamination removal' [patent_app_type] => utility [patent_app_number] => 11/019727 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3756 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/247/07247579.pdf [firstpage_image] =>[orig_patent_app_number] => 11019727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019727
Cleaning methods for silicon electrode assembly surface contamination removal Dec 22, 2004 Issued
Array ( [id] => 5656025 [patent_doc_number] => 20060141761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process' [patent_app_type] => utility [patent_app_number] => 11/020907 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141761.pdf [firstpage_image] =>[orig_patent_app_number] => 11020907 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020907
System for and method of forming via holes by multiple deposition events in a continuous inline shadow mask deposition process Dec 22, 2004 Issued
Array ( [id] => 544111 [patent_doc_number] => 07163884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Semiconductor device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/020327 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/163/07163884.pdf [firstpage_image] =>[orig_patent_app_number] => 11020327 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020327
Semiconductor device and fabrication method thereof Dec 21, 2004 Issued
Array ( [id] => 6983469 [patent_doc_number] => 20050153539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method of forming interconnection lines in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/012687 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153539.pdf [firstpage_image] =>[orig_patent_app_number] => 11012687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012687
Method of forming interconnection lines in a semiconductor device Dec 15, 2004 Abandoned
Array ( [id] => 6944916 [patent_doc_number] => 20050196965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/006187 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2330 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20050196965.pdf [firstpage_image] =>[orig_patent_app_number] => 11006187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/006187
Method for manufacturing semiconductor device Dec 6, 2004 Issued
Array ( [id] => 820558 [patent_doc_number] => 07407889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Method of manufacturing article having uneven surface' [patent_app_type] => utility [patent_app_number] => 10/993587 [patent_app_country] => US [patent_app_date] => 2004-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 36 [patent_no_of_words] => 5323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/407/07407889.pdf [firstpage_image] =>[orig_patent_app_number] => 10993587 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/993587
Method of manufacturing article having uneven surface Nov 18, 2004 Issued
Array ( [id] => 559326 [patent_doc_number] => 07161183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Liquid crystal display and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/982129 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 44 [patent_no_of_words] => 6857 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/161/07161183.pdf [firstpage_image] =>[orig_patent_app_number] => 10982129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982129
Liquid crystal display and method of manufacturing the same Nov 4, 2004 Issued
Array ( [id] => 7010933 [patent_doc_number] => 20050064649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/983239 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064649.pdf [firstpage_image] =>[orig_patent_app_number] => 10983239 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/983239
Semiconductor device and method for manufacturing the same Nov 4, 2004 Abandoned
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