John P. Trimmings

Array ( [id] => 6449943 [patent_doc_number] => 20100153801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'METHOD FOR AT SPEED TESTING OF DEVICES' [patent_app_type] => utility [patent_app_number] => 12/714833 [patent_app_country] => US [patent_app_date] => 2010-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9599 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153801.pdf [firstpage_image] =>[orig_patent_app_number] => 12714833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9156852 [patent_doc_number] => 08589766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Codeword remapping schemes for non-volatile memories' [patent_app_type] => utility [patent_app_number] => 12/711418 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9900 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12711418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6534155 [patent_doc_number] => 20100218073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Resistive Memory Devices and Methods of Controlling Operations of the Same' [patent_app_type] => utility [patent_app_number] => 12/711416 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8382 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218073.pdf [firstpage_image] =>[orig_patent_app_number] => 12711416 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8438257 [patent_doc_number] => 08286042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testability' [patent_app_type] => utility [patent_app_number] => 12/710081 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3313 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12710081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8529467 [patent_doc_number] => 08306049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Multicast subscription based on forward error correction' [patent_app_type] => utility [patent_app_number] => 12/709776 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4602 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12709776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8530665 [patent_doc_number] => 08307249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'At-speed bitmapping in a memory built-in self-test by locking an N-TH failure' [patent_app_type] => utility [patent_app_number] => 12/709565 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7818 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12709565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6524716 [patent_doc_number] => 20100211845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'METHOD FOR PERFORMING HYBRID AUTOMATIC REPEAT REQUEST OPERATION IN A WIRELESS MOBILE COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/708060 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 19604 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20100211845.pdf [firstpage_image] =>[orig_patent_app_number] => 12708060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8366699 [patent_doc_number] => 08255780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding' [patent_app_type] => utility [patent_app_number] => 12/708323 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7716 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12708323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6565180 [patent_doc_number] => 20100223518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Diagnostic mode switching' [patent_app_type] => utility [patent_app_number] => 12/656434 [patent_app_country] => US [patent_app_date] => 2010-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4144 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223518.pdf [firstpage_image] =>[orig_patent_app_number] => 12656434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4479495 [patent_doc_number] => 07945824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Processor-memory unit for use in system-in-package and system-in-module devices' [patent_app_type] => utility [patent_app_number] => 12/646540 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3983 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/945/07945824.pdf [firstpage_image] =>[orig_patent_app_number] => 12646540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8798305 [patent_doc_number] => 08437183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-07 [patent_title] => 'Auxiliary parity bits for data written in multi-level cells' [patent_app_type] => utility [patent_app_number] => 13/122469 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9036 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13122469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6647204 [patent_doc_number] => 20100174956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Semiconductor integrated circuit and method of saving and restoring internal state of the same' [patent_app_type] => utility [patent_app_number] => 12/654267 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174956.pdf [firstpage_image] =>[orig_patent_app_number] => 12654267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8594911 [patent_doc_number] => 08352794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Control of clock gating' [patent_app_type] => utility [patent_app_number] => 12/591430 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5866 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12591430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9257854 [patent_doc_number] => 08621295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Circuit module, semiconductor integrated circuit, and inspection apparatus and method thereof' [patent_app_type] => utility [patent_app_number] => 12/620727 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 10835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12620727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6227767 [patent_doc_number] => 20100058124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'SYSTEM AND METHOD FOR INITIALIZING A MEMORY SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME' [patent_app_type] => utility [patent_app_number] => 12/618429 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20100058124.pdf [firstpage_image] =>[orig_patent_app_number] => 12618429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6218069 [patent_doc_number] => 20100053334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'Panel Driving Circuit that Generates Panel Test Pattern and Panel Test Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/616466 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4542 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20100053334.pdf [firstpage_image] =>[orig_patent_app_number] => 12616466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6241174 [patent_doc_number] => 20100269001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'TESTING SYSTEM AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/616149 [patent_app_country] => US [patent_app_date] => 2009-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4318 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269001.pdf [firstpage_image] =>[orig_patent_app_number] => 12616149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7684008 [patent_doc_number] => 20100122133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'LATCH CIRCUIT INCLUDING DATA INPUT TERMINAL AND SCAN DATA INPUT TERMINAL, AND SEMICONDUCTOR DEVICE AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/607627 [patent_app_country] => US [patent_app_date] => 2009-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5006 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20100122133.pdf [firstpage_image] =>[orig_patent_app_number] => 12607627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8033727 [patent_doc_number] => 08145959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Systems and methods for measuring soft errors and soft error rates in an application specific integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/604643 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/145/08145959.pdf [firstpage_image] =>[orig_patent_app_number] => 12604643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9023581 [patent_doc_number] => 08533579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Data loss detection method for handling fuzziness in sensitive keywords' [patent_app_type] => utility [patent_app_number] => 12/603465 [patent_app_country] => US [patent_app_date] => 2009-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12603465 [rel_patent_id] =>[rel_patent_doc_number] =>)