Search

John P. Trimmings

Examiner (ID: 6692)

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138
Total Applications
878
Issued Applications
745
Pending Applications
10
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 28400 [patent_doc_number] => 07797591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Semiconductor integrated circuit, design support software system, and automatic test pattern generation system' [patent_app_type] => utility [patent_app_number] => 12/503336 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6928 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797591.pdf [firstpage_image] =>[orig_patent_app_number] => 12503336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503336
Semiconductor integrated circuit, design support software system, and automatic test pattern generation system Jul 14, 2009 Issued
Array ( [id] => 7982753 [patent_doc_number] => 08074135 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-06 [patent_title] => 'Apparatus and method for testing and debugging an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/500245 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3316 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074135.pdf [firstpage_image] =>[orig_patent_app_number] => 12500245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500245
Apparatus and method for testing and debugging an integrated circuit Jul 8, 2009 Issued
Array ( [id] => 7547988 [patent_doc_number] => 08055969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Multi-strobe circuit' [patent_app_type] => utility [patent_app_number] => 12/498781 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3946 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055969.pdf [firstpage_image] =>[orig_patent_app_number] => 12498781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498781
Multi-strobe circuit Jul 6, 2009 Issued
Array ( [id] => 7510588 [patent_doc_number] => 08037375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Fast data eye retraining for a memory' [patent_app_type] => utility [patent_app_number] => 12/459420 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4024 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037375.pdf [firstpage_image] =>[orig_patent_app_number] => 12459420 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/459420
Fast data eye retraining for a memory Jun 29, 2009 Issued
Array ( [id] => 7982745 [patent_doc_number] => 08074131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Generic debug external connection (GDXC) for high integration integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/495583 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5407 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074131.pdf [firstpage_image] =>[orig_patent_app_number] => 12495583 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495583
Generic debug external connection (GDXC) for high integration integrated circuits Jun 29, 2009 Issued
Array ( [id] => 7803789 [patent_doc_number] => 08132073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-06 [patent_title] => 'Distributed storage system with enhanced security' [patent_app_type] => utility [patent_app_number] => 12/495189 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 12749 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/132/08132073.pdf [firstpage_image] =>[orig_patent_app_number] => 12495189 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495189
Distributed storage system with enhanced security Jun 29, 2009 Issued
Array ( [id] => 6363715 [patent_doc_number] => 20100332931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Method for Speeding Up Serial Data Tolerance Testing' [patent_app_type] => utility [patent_app_number] => 12/494624 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332931.pdf [firstpage_image] =>[orig_patent_app_number] => 12494624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494624
Method for speeding up serial data tolerance testing Jun 29, 2009 Issued
Array ( [id] => 8011053 [patent_doc_number] => 08086944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Hard disk drive with data error recovery using multiple reads and derived reliability information' [patent_app_type] => utility [patent_app_number] => 12/493925 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2051 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086944.pdf [firstpage_image] =>[orig_patent_app_number] => 12493925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493925
Hard disk drive with data error recovery using multiple reads and derived reliability information Jun 28, 2009 Issued
Array ( [id] => 5467786 [patent_doc_number] => 20090327986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'GENERATING RESPONSES TO PATTERNS STIMULATING AN ELECTRONIC CIRCUIT WITH TIMING EXCEPTION PATHS' [patent_app_type] => utility [patent_app_number] => 12/494121 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14149 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327986.pdf [firstpage_image] =>[orig_patent_app_number] => 12494121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494121
Generating responses to patterns stimulating an electronic circuit with timing exception paths Jun 28, 2009 Issued
Array ( [id] => 7525039 [patent_doc_number] => 08028209 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Scalable scan system for system-on-chip design' [patent_app_type] => utility [patent_app_number] => 12/493050 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8665 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028209.pdf [firstpage_image] =>[orig_patent_app_number] => 12493050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493050
Scalable scan system for system-on-chip design Jun 25, 2009 Issued
Array ( [id] => 7798484 [patent_doc_number] => 08127202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-28 [patent_title] => 'Use of alternative value in cell detection' [patent_app_type] => utility [patent_app_number] => 12/489618 [patent_app_country] => US [patent_app_date] => 2009-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 17826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/127/08127202.pdf [firstpage_image] =>[orig_patent_app_number] => 12489618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/489618
Use of alternative value in cell detection Jun 22, 2009 Issued
Array ( [id] => 9781380 [patent_doc_number] => 08856603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Method for detecting and correcting errors for a memory whose structure shows dissymmetrical behavior, corresponding memory and its use' [patent_app_type] => utility [patent_app_number] => 12/999485 [patent_app_country] => US [patent_app_date] => 2009-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5075 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12999485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/999485
Method for detecting and correcting errors for a memory whose structure shows dissymmetrical behavior, corresponding memory and its use Jun 17, 2009 Issued
Array ( [id] => 7521084 [patent_doc_number] => 07975193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Solid state storage end of life prediction with correction history' [patent_app_type] => utility [patent_app_number] => 12/475716 [patent_app_country] => US [patent_app_date] => 2009-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975193.pdf [firstpage_image] =>[orig_patent_app_number] => 12475716 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/475716
Solid state storage end of life prediction with correction history May 31, 2009 Issued
Array ( [id] => 6414530 [patent_doc_number] => 20100306604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHOD AND CIRCUIT FOR BROWNOUT DETECTION IN A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/473934 [patent_app_country] => US [patent_app_date] => 2009-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20100306604.pdf [firstpage_image] =>[orig_patent_app_number] => 12473934 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/473934
Method and circuit for brownout detection in a memory system May 27, 2009 Issued
Array ( [id] => 5305796 [patent_doc_number] => 20090300448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'SCAN FLIP-FLOP DEVICE' [patent_app_type] => utility [patent_app_number] => 12/466600 [patent_app_country] => US [patent_app_date] => 2009-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5992 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300448.pdf [firstpage_image] =>[orig_patent_app_number] => 12466600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/466600
SCAN FLIP-FLOP DEVICE May 14, 2009 Abandoned
Array ( [id] => 6463738 [patent_doc_number] => 20100281347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'VITERBI DETECTOR THAT ASSOCIATES MULTIPLE DATA DEPENDENT NOISE PREDICTION FILTERS WITH EACH POSSIBLE BIT PATTERN' [patent_app_type] => utility [patent_app_number] => 12/434958 [patent_app_country] => US [patent_app_date] => 2009-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281347.pdf [firstpage_image] =>[orig_patent_app_number] => 12434958 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/434958
Viterbi detector that associates multiple data dependent noise prediction filters with each possible bit pattern May 3, 2009 Issued
Array ( [id] => 8472778 [patent_doc_number] => 08301971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Digital broadcasting system and error correction method thereof' [patent_app_type] => utility [patent_app_number] => 12/434643 [patent_app_country] => US [patent_app_date] => 2009-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6857 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12434643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/434643
Digital broadcasting system and error correction method thereof May 1, 2009 Issued
Array ( [id] => 8540540 [patent_doc_number] => 08316267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Error concealment' [patent_app_type] => utility [patent_app_number] => 12/434449 [patent_app_country] => US [patent_app_date] => 2009-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8968 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12434449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/434449
Error concealment Apr 30, 2009 Issued
Array ( [id] => 4479487 [patent_doc_number] => 07945822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-17 [patent_title] => 'Storing data to multi-chip low-latency random read memory device using non-aligned striping' [patent_app_type] => utility [patent_app_number] => 12/430783 [patent_app_country] => US [patent_app_date] => 2009-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14507 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/945/07945822.pdf [firstpage_image] =>[orig_patent_app_number] => 12430783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/430783
Storing data to multi-chip low-latency random read memory device using non-aligned striping Apr 26, 2009 Issued
Array ( [id] => 5317703 [patent_doc_number] => 20090282301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'APPARATUS, SYSTEM, AND METHOD FOR BAD BLOCK REMAPPING' [patent_app_type] => utility [patent_app_number] => 12/419223 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11764 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282301.pdf [firstpage_image] =>[orig_patent_app_number] => 12419223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/419223
Apparatus, system, and method for bad block remapping Apr 5, 2009 Issued
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