Search

John P. Trimmings

Examiner (ID: 12550)

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138
Total Applications
878
Issued Applications
745
Pending Applications
10
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 47851 [patent_doc_number] => 07783938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-24 [patent_title] => 'Result directed diagnostic method and system' [patent_app_type] => utility [patent_app_number] => 12/183311 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5202 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/783/07783938.pdf [firstpage_image] =>[orig_patent_app_number] => 12183311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183311
Result directed diagnostic method and system Jul 30, 2008 Issued
Array ( [id] => 6565259 [patent_doc_number] => 20100017668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING' [patent_app_type] => utility [patent_app_number] => 12/173651 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017668.pdf [firstpage_image] =>[orig_patent_app_number] => 12173651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/173651
System and method for digital logic testing Jul 14, 2008 Issued
Array ( [id] => 6511450 [patent_doc_number] => 20100011279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Error correcting viterbi decoder' [patent_app_type] => utility [patent_app_number] => 12/218183 [patent_app_country] => US [patent_app_date] => 2008-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20100011279.pdf [firstpage_image] =>[orig_patent_app_number] => 12218183 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/218183
Error correcting Viterbi decoder Jul 10, 2008 Issued
Array ( [id] => 5484226 [patent_doc_number] => 20090273991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND COMPRESSION TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/165094 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12642 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20090273991.pdf [firstpage_image] =>[orig_patent_app_number] => 12165094 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165094
Semiconductor memory device, operating method thereof, and compression test method thereof Jun 29, 2008 Issued
Array ( [id] => 4889084 [patent_doc_number] => 20080263416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'METHOD AND APPARATUS TO ADJUST VOLTAGE FOR STORAGE LOCATION RELIABILITY' [patent_app_type] => utility [patent_app_number] => 12/163618 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263416.pdf [firstpage_image] =>[orig_patent_app_number] => 12163618 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163618
Method and apparatus to adjust voltage for storage location reliability Jun 26, 2008 Issued
Array ( [id] => 69063 [patent_doc_number] => 07761753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Memory channel with bit lane fail-over' [patent_app_type] => utility [patent_app_number] => 12/136028 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 12151 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761753.pdf [firstpage_image] =>[orig_patent_app_number] => 12136028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136028
Memory channel with bit lane fail-over Jun 8, 2008 Issued
Array ( [id] => 47855 [patent_doc_number] => 07783940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Apparatus for redundancy reconfiguration of faculty memories' [patent_app_type] => utility [patent_app_number] => 12/155596 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2292 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/783/07783940.pdf [firstpage_image] =>[orig_patent_app_number] => 12155596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155596
Apparatus for redundancy reconfiguration of faculty memories Jun 5, 2008 Issued
Array ( [id] => 116678 [patent_doc_number] => 07721167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-18 [patent_title] => 'Apparatus and method for testing and debugging an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/154896 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8656 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721167.pdf [firstpage_image] =>[orig_patent_app_number] => 12154896 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/154896
Apparatus and method for testing and debugging an integrated circuit May 27, 2008 Issued
Array ( [id] => 5312045 [patent_doc_number] => 20090019326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Self-synchronizing bit error analyzer and circuit' [patent_app_type] => utility [patent_app_number] => 12/154188 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5748 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019326.pdf [firstpage_image] =>[orig_patent_app_number] => 12154188 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/154188
Self-synchronizing bit error analyzer and circuit May 20, 2008 Issued
Array ( [id] => 5317705 [patent_doc_number] => 20090282303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/118477 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282303.pdf [firstpage_image] =>[orig_patent_app_number] => 12118477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/118477
Built in test controller with a downloadable testing program May 8, 2008 Issued
Array ( [id] => 4757142 [patent_doc_number] => 20080309367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SEMICONDUCTOR INTEGRATED DEVICE' [patent_app_type] => utility [patent_app_number] => 12/115691 [patent_app_country] => US [patent_app_date] => 2008-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4829 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20080309367.pdf [firstpage_image] =>[orig_patent_app_number] => 12115691 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/115691
SEMICONDUCTOR INTEGRATED DEVICE May 5, 2008 Abandoned
Array ( [id] => 4559820 [patent_doc_number] => 07877668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Memory access system' [patent_app_type] => utility [patent_app_number] => 12/115098 [patent_app_country] => US [patent_app_date] => 2008-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5860 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877668.pdf [firstpage_image] =>[orig_patent_app_number] => 12115098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/115098
Memory access system May 4, 2008 Issued
Array ( [id] => 4500118 [patent_doc_number] => 07904768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Probing system for integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 12/114768 [patent_app_country] => US [patent_app_date] => 2008-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2914 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904768.pdf [firstpage_image] =>[orig_patent_app_number] => 12114768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114768
Probing system for integrated circuit devices May 2, 2008 Issued
Array ( [id] => 7686348 [patent_doc_number] => 20090177943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'ERROR CORRECTION CODING USING SOFT INFORMATION AND INTERLEAVING' [patent_app_type] => utility [patent_app_number] => 12/114066 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177943.pdf [firstpage_image] =>[orig_patent_app_number] => 12114066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114066
ERROR CORRECTION CODING USING SOFT INFORMATION AND INTERLEAVING May 1, 2008 Abandoned
Array ( [id] => 8158374 [patent_doc_number] => 08171372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Feedback signaling error detection and checking in MIMO wireless communication systems' [patent_app_type] => utility [patent_app_number] => 12/112636 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7599 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171372.pdf [firstpage_image] =>[orig_patent_app_number] => 12112636 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112636
Feedback signaling error detection and checking in MIMO wireless communication systems Apr 29, 2008 Issued
Array ( [id] => 5266884 [patent_doc_number] => 20090119569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Encoding system and method for encoding error control codes within bit streams' [patent_app_type] => utility [patent_app_number] => 12/149214 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119569.pdf [firstpage_image] =>[orig_patent_app_number] => 12149214 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149214
Encoding system and method for encoding error control codes within bit streams Apr 28, 2008 Issued
Array ( [id] => 5535358 [patent_doc_number] => 20090235146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Systems and Methods for Using Intrinsic Data for Regenerating Data from a Defective Medium' [patent_app_type] => utility [patent_app_number] => 12/111867 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235146.pdf [firstpage_image] =>[orig_patent_app_number] => 12111867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111867
Systems and methods for using intrinsic data for regenerating data from a defective medium Apr 28, 2008 Issued
Array ( [id] => 8170880 [patent_doc_number] => 08176402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Decoding apparatus, decoding method, and decoding program' [patent_app_type] => utility [patent_app_number] => 12/110064 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 13565 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176402.pdf [firstpage_image] =>[orig_patent_app_number] => 12110064 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110064
Decoding apparatus, decoding method, and decoding program Apr 24, 2008 Issued
Array ( [id] => 4587031 [patent_doc_number] => 07849387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Detecting architectural vulnerability of processor resources' [patent_app_type] => utility [patent_app_number] => 12/148812 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7921 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849387.pdf [firstpage_image] =>[orig_patent_app_number] => 12148812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/148812
Detecting architectural vulnerability of processor resources Apr 22, 2008 Issued
Array ( [id] => 4678315 [patent_doc_number] => 20080215946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY TEST METHOD' [patent_app_type] => utility [patent_app_number] => 12/098987 [patent_app_country] => US [patent_app_date] => 2008-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13759 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20080215946.pdf [firstpage_image] =>[orig_patent_app_number] => 12098987 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/098987
Semiconductor integrated circuit and memory test method Apr 6, 2008 Issued
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