
John P. Trimmings
Examiner (ID: 12550)
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2117, 2133, 2138 |
| Total Applications | 878 |
| Issued Applications | 745 |
| Pending Applications | 10 |
| Abandoned Applications | 127 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 325283
[patent_doc_number] => 07519889
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-04-14
[patent_title] => 'System and method to reduce LBIST manufacturing test time of integrated circuits'
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[patent_app_number] => 12/060339
[patent_app_country] => US
[patent_app_date] => 2008-04-01
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[pdf_file] => patents/07/519/07519889.pdf
[firstpage_image] =>[orig_patent_app_number] => 12060339
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/060339 | System and method to reduce LBIST manufacturing test time of integrated circuits | Mar 31, 2008 | Issued |
Array
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[patent_doc_number] => 20080189584
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[patent_kind] => A1
[patent_issue_date] => 2008-08-07
[patent_title] => 'SYSTEM AND APPARATUS FOR IMPROVING LOGICAL BUILT-IN SELF TEST (LBIST) AC FAULT ISOLATIONS'
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Array
(
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[patent_title] => 'CAN system'
[patent_app_type] => utility
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[patent_app_date] => 2008-03-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/076980 | CAN system | Mar 25, 2008 | Issued |
Array
(
[id] => 193000
[patent_doc_number] => 07644327
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[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA'
[patent_app_type] => utility
[patent_app_number] => 12/049166
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Array
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[patent_title] => 'Methods and apparatuses for generating a random sequence of commands for a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/039292
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[patent_app_date] => 2008-02-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/039292 | Methods and apparatuses for generating a random sequence of commands for a semiconductor device | Feb 27, 2008 | Issued |
Array
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[patent_title] => 'METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT INVOLVING ERROR THRESHOLDS'
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Array
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[patent_title] => 'AC ABIST Diagnostic Method, Apparatus and Program Product'
[patent_app_type] => utility
[patent_app_number] => 12/035515
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/035515 | AC ABIST diagnostic method, apparatus and program product | Feb 21, 2008 | Issued |
Array
(
[id] => 4600764
[patent_doc_number] => 07984350
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-19
[patent_title] => 'Logic circuitry and recording medium'
[patent_app_type] => utility
[patent_app_number] => 12/035884
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/035884 | Logic circuitry and recording medium | Feb 21, 2008 | Issued |
Array
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[id] => 5393433
[patent_doc_number] => 20090210746
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[patent_issue_date] => 2009-08-20
[patent_title] => 'GENERATING TEST COVERAGE BIN BASED ON SIMULATION RESULT'
[patent_app_type] => utility
[patent_app_number] => 12/033239
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[patent_app_date] => 2008-02-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033239 | Generating test coverage bin based on simulation result | Feb 18, 2008 | Issued |
Array
(
[id] => 5393448
[patent_doc_number] => 20090210761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-20
[patent_title] => 'AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification Patterns'
[patent_app_type] => utility
[patent_app_number] => 12/031930
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[patent_app_date] => 2008-02-15
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Array
(
[id] => 4522841
[patent_doc_number] => 07917821
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[patent_issue_date] => 2011-03-29
[patent_title] => 'System-on-chip performing multi-phase scan chain and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/071106 | System-on-chip performing multi-phase scan chain and method thereof | Feb 14, 2008 | Issued |
Array
(
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[patent_title] => 'System for a Combined Error Correction Code and Cyclic Redundancy Check Code for a Memory Channel'
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Array
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Array
(
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[patent_title] => 'RETRANSMISSION OF ERRONEOUS DATA'
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Array
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Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/016577 | Error correction system and method | Jan 17, 2008 | Issued |