Search

John P. Trimmings

Examiner (ID: 12550)

Most Active Art Unit
2117
Art Unit(s)
2117, 2133, 2138
Total Applications
878
Issued Applications
745
Pending Applications
10
Abandoned Applications
127

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 97447 [patent_doc_number] => 07739573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Voltage identifier sorting' [patent_app_type] => utility [patent_app_number] => 11/621766 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739573.pdf [firstpage_image] =>[orig_patent_app_number] => 11621766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621766
Voltage identifier sorting Jan 9, 2007 Issued
Array ( [id] => 58732 [patent_doc_number] => 07770080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Using neighborhood functions to extract logical models of physical failures using layout based diagnosis' [patent_app_type] => utility [patent_app_number] => 11/651782 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8530 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/770/07770080.pdf [firstpage_image] =>[orig_patent_app_number] => 11651782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/651782
Using neighborhood functions to extract logical models of physical failures using layout based diagnosis Jan 9, 2007 Issued
Array ( [id] => 4928954 [patent_doc_number] => 20080168317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Linked Random Access Memory (RAM) Interleaved Pattern Persistence Strategy' [patent_app_type] => utility [patent_app_number] => 11/619626 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20080168317.pdf [firstpage_image] =>[orig_patent_app_number] => 11619626 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619626
Linked random access memory (RAM) interleaved pattern persistence strategy Jan 3, 2007 Issued
Array ( [id] => 97023 [patent_doc_number] => 07734973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Testing apparatus and testing method for an integrated circuit, and integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/647363 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 17413 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/734/07734973.pdf [firstpage_image] =>[orig_patent_app_number] => 11647363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647363
Testing apparatus and testing method for an integrated circuit, and integrated circuit Dec 28, 2006 Issued
Array ( [id] => 7532642 [patent_doc_number] => 07844876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Temperature sampling in electronic devices' [patent_app_type] => utility [patent_app_number] => 11/648122 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4165 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844876.pdf [firstpage_image] =>[orig_patent_app_number] => 11648122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648122
Temperature sampling in electronic devices Dec 28, 2006 Issued
Array ( [id] => 5017743 [patent_doc_number] => 20070260952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'DFT TECHNIQUES TO REDUCE TEST TIME AND POWER FOR SoCs' [patent_app_type] => utility [patent_app_number] => 11/617764 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6528 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20070260952.pdf [firstpage_image] =>[orig_patent_app_number] => 11617764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/617764
DFT techniques to reduce test time and power for SoCs Dec 28, 2006 Issued
Array ( [id] => 180082 [patent_doc_number] => 07657798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Semiconductor integrated circuit and the same checking method' [patent_app_type] => utility [patent_app_number] => 11/645509 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657798.pdf [firstpage_image] =>[orig_patent_app_number] => 11645509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645509
Semiconductor integrated circuit and the same checking method Dec 26, 2006 Issued
Array ( [id] => 4686930 [patent_doc_number] => 20080031111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Verification method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/643813 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11904 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20080031111.pdf [firstpage_image] =>[orig_patent_app_number] => 11643813 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643813
Verification method and apparatus Dec 21, 2006 Issued
Array ( [id] => 5024810 [patent_doc_number] => 20070150777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Memory test circuit and method' [patent_app_type] => utility [patent_app_number] => 11/642898 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10540 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150777.pdf [firstpage_image] =>[orig_patent_app_number] => 11642898 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/642898
Memory test circuit and method Dec 20, 2006 Issued
Array ( [id] => 5221483 [patent_doc_number] => 20070162795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Test apparatus and test method' [patent_app_type] => utility [patent_app_number] => 11/643633 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4647 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20070162795.pdf [firstpage_image] =>[orig_patent_app_number] => 11643633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643633
Test apparatus and test method Dec 20, 2006 Abandoned
Array ( [id] => 261899 [patent_doc_number] => 07574633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Test apparatus, adjustment method and recording medium' [patent_app_type] => utility [patent_app_number] => 11/643010 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10974 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574633.pdf [firstpage_image] =>[orig_patent_app_number] => 11643010 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643010
Test apparatus, adjustment method and recording medium Dec 19, 2006 Issued
Array ( [id] => 4869060 [patent_doc_number] => 20080148119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Apparatus for Built-in Speed Grading and Method for Generating Desired Frequency for the Same' [patent_app_type] => utility [patent_app_number] => 11/612945 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4568 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148119.pdf [firstpage_image] =>[orig_patent_app_number] => 11612945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612945
Apparatus for Built-in Speed Grading and Method for Generating Desired Frequency for the Same Dec 18, 2006 Abandoned
Array ( [id] => 309682 [patent_doc_number] => 07533310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor memory test device and method thereof' [patent_app_type] => utility [patent_app_number] => 11/640893 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3719 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533310.pdf [firstpage_image] =>[orig_patent_app_number] => 11640893 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/640893
Semiconductor memory test device and method thereof Dec 18, 2006 Issued
Array ( [id] => 4522866 [patent_doc_number] => 07917825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Method and apparatus for selectively utilizing information within a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/639161 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5385 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917825.pdf [firstpage_image] =>[orig_patent_app_number] => 11639161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/639161
Method and apparatus for selectively utilizing information within a semiconductor device Dec 14, 2006 Issued
Array ( [id] => 4589802 [patent_doc_number] => 07861128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-28 [patent_title] => 'Scan element with self scan-mode toggle' [patent_app_type] => utility [patent_app_number] => 11/639996 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5236 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861128.pdf [firstpage_image] =>[orig_patent_app_number] => 11639996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/639996
Scan element with self scan-mode toggle Dec 13, 2006 Issued
Array ( [id] => 5510384 [patent_doc_number] => 20090083591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Method and Apparatus For Recording High-Speed Input Data Into a Matrix of Memory Devices' [patent_app_type] => utility [patent_app_number] => 12/087708 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3481 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083591.pdf [firstpage_image] =>[orig_patent_app_number] => 12087708 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/087708
Method and apparatus for recording high-speed input data into a matrix of memory devices Dec 3, 2006 Issued
Array ( [id] => 5189476 [patent_doc_number] => 20070167785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Diagnostic mode switching' [patent_app_type] => utility [patent_app_number] => 11/601849 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4175 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20070167785.pdf [firstpage_image] =>[orig_patent_app_number] => 11601849 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/601849
Diagnostic mode switching Nov 19, 2006 Issued
Array ( [id] => 600093 [patent_doc_number] => 07441169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Semiconductor integrated circuit with test circuit' [patent_app_type] => utility [patent_app_number] => 11/599263 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 22271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441169.pdf [firstpage_image] =>[orig_patent_app_number] => 11599263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/599263
Semiconductor integrated circuit with test circuit Nov 14, 2006 Issued
Array ( [id] => 332590 [patent_doc_number] => RE040684 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Fast cyclic redundancy check (CRC) generation' [patent_app_type] => reissue [patent_app_number] => 11/598156 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3040 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040684.pdf [firstpage_image] =>[orig_patent_app_number] => 11598156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/598156
Fast cyclic redundancy check (CRC) generation Nov 8, 2006 Issued
Array ( [id] => 4905613 [patent_doc_number] => 20080115027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Memory Model for Functional Verification of Multi-Processor Systems' [patent_app_type] => utility [patent_app_number] => 11/554053 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20080115027.pdf [firstpage_image] =>[orig_patent_app_number] => 11554053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554053
Memory model for functional verification of multi-processor systems Oct 29, 2006 Issued
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