Search

John S. Heyman

Examiner (ID: 4323)

Most Active Art Unit
2504
Art Unit(s)
2607, 2871, 3992, 2603, 2202, 2504, 2506
Total Applications
1362
Issued Applications
1294
Pending Applications
6
Abandoned Applications
62

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5695819 [patent_doc_number] => 20060155966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Processor including a register file and method for computing flush masks in a multi-threaded processing system' [patent_app_type] => utility [patent_app_number] => 11/324399 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3154 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155966.pdf [firstpage_image] =>[orig_patent_app_number] => 11324399 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324399
Processor including a register file and method for computing flush masks in a multi-threaded processing system Jan 2, 2006 Issued
Array ( [id] => 392850 [patent_doc_number] => 07302554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Methods and apparatus for multi-processor pipeline parallelism' [patent_app_type] => utility [patent_app_number] => 11/108959 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5642 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302554.pdf [firstpage_image] =>[orig_patent_app_number] => 11108959 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/108959
Methods and apparatus for multi-processor pipeline parallelism Apr 18, 2005 Issued
Array ( [id] => 404202 [patent_doc_number] => 07293161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-06 [patent_title] => 'Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode' [patent_app_type] => utility [patent_app_number] => 11/106180 [patent_app_country] => US [patent_app_date] => 2005-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4885 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/293/07293161.pdf [firstpage_image] =>[orig_patent_app_number] => 11106180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/106180
Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode Apr 12, 2005 Issued
Array ( [id] => 411421 [patent_doc_number] => 07287146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Array-type computer processor' [patent_app_type] => utility [patent_app_number] => 11/048071 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11080 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287146.pdf [firstpage_image] =>[orig_patent_app_number] => 11048071 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048071
Array-type computer processor Feb 1, 2005 Issued
Array ( [id] => 5633466 [patent_doc_number] => 20060149937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Register file regions for a processing system' [patent_app_type] => utility [patent_app_number] => 11/024298 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5155 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149937.pdf [firstpage_image] =>[orig_patent_app_number] => 11024298 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024298
Register file regions for a processing system Dec 27, 2004 Issued
Array ( [id] => 469376 [patent_doc_number] => 07240184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations' [patent_app_type] => utility [patent_app_number] => 10/985695 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 24358 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240184.pdf [firstpage_image] =>[orig_patent_app_number] => 10985695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985695
Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations Nov 9, 2004 Issued
Array ( [id] => 5809358 [patent_doc_number] => 20060095714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Clip instruction for processor' [patent_app_type] => utility [patent_app_number] => 10/982662 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4774 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095714.pdf [firstpage_image] =>[orig_patent_app_number] => 10982662 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982662
Clip instruction for processor Nov 2, 2004 Abandoned
Array ( [id] => 5809379 [patent_doc_number] => 20060095735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Systems and methods for increasing register addressing space in instruction-width limited processors' [patent_app_type] => utility [patent_app_number] => 10/978342 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3338 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095735.pdf [firstpage_image] =>[orig_patent_app_number] => 10978342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978342
Systems for increasing register addressing space in instruction-width limited processors Oct 31, 2004 Issued
Array ( [id] => 5809465 [patent_doc_number] => 20060095821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Executing checker instructions in redundant multithreading environments' [patent_app_type] => utility [patent_app_number] => 10/953887 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2279 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095821.pdf [firstpage_image] =>[orig_patent_app_number] => 10953887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/953887
Implementing check instructions in each thread within a redundant multithreading environments Sep 28, 2004 Issued
Array ( [id] => 396740 [patent_doc_number] => 07299339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework' [patent_app_type] => utility [patent_app_number] => 10/931068 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5096 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299339.pdf [firstpage_image] =>[orig_patent_app_number] => 10931068 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931068
Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework Aug 29, 2004 Issued
Array ( [id] => 465928 [patent_doc_number] => 07243212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Processor-controller interface for non-lock step operation' [patent_app_type] => utility [patent_app_number] => 10/913991 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 27548 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243212.pdf [firstpage_image] =>[orig_patent_app_number] => 10913991 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/913991
Processor-controller interface for non-lock step operation Aug 5, 2004 Issued
Array ( [id] => 7063210 [patent_doc_number] => 20050005086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Pipeline processing device and interrupt processing method' [patent_app_type] => utility [patent_app_number] => 10/854146 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5081 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20050005086.pdf [firstpage_image] =>[orig_patent_app_number] => 10854146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/854146
Pipeline processing device and interrupt processing method May 26, 2004 Issued
Array ( [id] => 407199 [patent_doc_number] => 07290123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'System, device and method of maintaining in an array loop iteration data related to branch entries of a loop detector' [patent_app_type] => utility [patent_app_number] => 10/849025 [patent_app_country] => US [patent_app_date] => 2004-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2347 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290123.pdf [firstpage_image] =>[orig_patent_app_number] => 10849025 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/849025
System, device and method of maintaining in an array loop iteration data related to branch entries of a loop detector May 19, 2004 Issued
Array ( [id] => 524750 [patent_doc_number] => 07197630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation' [patent_app_type] => utility [patent_app_number] => 10/822468 [patent_app_country] => US [patent_app_date] => 2004-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10446 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197630.pdf [firstpage_image] =>[orig_patent_app_number] => 10822468 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822468
Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation Apr 11, 2004 Issued
Array ( [id] => 6953877 [patent_doc_number] => 20050228972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Completion table configured to track a larger number of outstanding instructions' [patent_app_type] => utility [patent_app_number] => 10/821054 [patent_app_country] => US [patent_app_date] => 2004-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7394 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20050228972.pdf [firstpage_image] =>[orig_patent_app_number] => 10821054 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/821054
Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table Apr 7, 2004 Issued
Array ( [id] => 6985304 [patent_doc_number] => 20050154864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method and apparatus for nested control flow' [patent_app_type] => utility [patent_app_number] => 10/756853 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3223 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20050154864.pdf [firstpage_image] =>[orig_patent_app_number] => 10756853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/756853
Method and apparatus for nested control flow of instructions using context information and instructions having extra bits Jan 13, 2004 Issued
Array ( [id] => 6985705 [patent_doc_number] => 20050155022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Method and apparatus for counting instruction execution and data accesses to identify hot spots' [patent_app_type] => utility [patent_app_number] => 10/757248 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 30945 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20050155022.pdf [firstpage_image] =>[orig_patent_app_number] => 10757248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757248
Method and apparatus for counting instruction execution and data accesses to identify hot spots Jan 13, 2004 Abandoned
Array ( [id] => 6985311 [patent_doc_number] => 20050154867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Autonomic method and apparatus for counting branch instructions to improve branch predictions' [patent_app_type] => utility [patent_app_number] => 10/757237 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6420 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20050154867.pdf [firstpage_image] =>[orig_patent_app_number] => 10757237 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757237
Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions Jan 13, 2004 Issued
Array ( [id] => 554153 [patent_doc_number] => 07181599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Method and apparatus for autonomic detection of cache “chase tail” conditions and storage of instructions/data in “chase tail” data structure' [patent_app_type] => utility [patent_app_number] => 10/757256 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 52 [patent_no_of_words] => 30899 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181599.pdf [firstpage_image] =>[orig_patent_app_number] => 10757256 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757256
Method and apparatus for autonomic detection of cache “chase tail” conditions and storage of instructions/data in “chase tail” data structure Jan 13, 2004 Issued
Array ( [id] => 7077155 [patent_doc_number] => 20050149691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Processing element with next and previous neighbor registers' [patent_app_type] => utility [patent_app_number] => 10/746564 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2353 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149691.pdf [firstpage_image] =>[orig_patent_app_number] => 10746564 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746564
Processing element with next and previous neighbor registers for direct data transfer Dec 23, 2003 Issued
Menu