Search

John S. Maples

Examiner (ID: 4144)

Most Active Art Unit
1745
Art Unit(s)
1728, 1795, 1723, 2202, 2201, 2203, 1104, 1111, 1745, 1754, 1107, 1741
Total Applications
2365
Issued Applications
1877
Pending Applications
115
Abandoned Applications
375

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2643716 [patent_doc_number] => 04953125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Semiconductor memory device having improved connecting structure of bit line and memory cell' [patent_app_type] => 1 [patent_app_number] => 7/173749 [patent_app_country] => US [patent_app_date] => 1988-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3072 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/953/04953125.pdf [firstpage_image] =>[orig_patent_app_number] => 173749 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/173749
Semiconductor memory device having improved connecting structure of bit line and memory cell Mar 24, 1988 Issued
Array ( [id] => 2549542 [patent_doc_number] => 04804816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-14 [patent_title] => 'Method of making a thin-film magnetic head having a multi-layered coil structure' [patent_app_type] => 1 [patent_app_number] => 7/165076 [patent_app_country] => US [patent_app_date] => 1988-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2343 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/804/04804816.pdf [firstpage_image] =>[orig_patent_app_number] => 165076 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/165076
Method of making a thin-film magnetic head having a multi-layered coil structure Mar 6, 1988 Issued
Array ( [id] => 2633528 [patent_doc_number] => 04956820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'Arbiter circuit for establishing priority control of read, write and refresh operations with respect to memory array' [patent_app_type] => 1 [patent_app_number] => 7/161059 [patent_app_country] => US [patent_app_date] => 1988-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6617 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956820.pdf [firstpage_image] =>[orig_patent_app_number] => 161059 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/161059
Arbiter circuit for establishing priority control of read, write and refresh operations with respect to memory array Feb 25, 1988 Issued
Array ( [id] => 2595478 [patent_doc_number] => 04926378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Bipolar static RAM having two wiring lines for each word line' [patent_app_type] => 1 [patent_app_number] => 7/160259 [patent_app_country] => US [patent_app_date] => 1988-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8935 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/926/04926378.pdf [firstpage_image] =>[orig_patent_app_number] => 160259 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/160259
Bipolar static RAM having two wiring lines for each word line Feb 24, 1988 Issued
Array ( [id] => 2676892 [patent_doc_number] => 04935901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-19 [patent_title] => 'Semiconductor memory with divided bit load and data bus lines' [patent_app_type] => 1 [patent_app_number] => 7/158259 [patent_app_country] => US [patent_app_date] => 1988-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3726 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/935/04935901.pdf [firstpage_image] =>[orig_patent_app_number] => 158259 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/158259
Semiconductor memory with divided bit load and data bus lines Feb 18, 1988 Issued
07/152789 ELECTRICALLY-ERASABLE, ELECTRICALLY-PROGRAMMABLE READ-ONLY MEMORY CELL Feb 4, 1988 Abandoned
Array ( [id] => 2420932 [patent_doc_number] => 04787006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-22 [patent_title] => 'Shutter pin groove for a magnetic disc cartridge' [patent_app_type] => 1 [patent_app_number] => 7/153497 [patent_app_country] => US [patent_app_date] => 1988-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2062 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/787/04787006.pdf [firstpage_image] =>[orig_patent_app_number] => 153497 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/153497
Shutter pin groove for a magnetic disc cartridge Feb 2, 1988 Issued
Array ( [id] => 2628634 [patent_doc_number] => 04894802 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-16 [patent_title] => 'Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase' [patent_app_type] => 1 [patent_app_number] => 7/151379 [patent_app_country] => US [patent_app_date] => 1988-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3676 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/894/04894802.pdf [firstpage_image] =>[orig_patent_app_number] => 151379 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/151379
Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase Feb 1, 1988 Issued
Array ( [id] => 2531517 [patent_doc_number] => 04878201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Semiconductor memory device having an improved timing signal generator for the column selection circuit' [patent_app_type] => 1 [patent_app_number] => 7/149269 [patent_app_country] => US [patent_app_date] => 1988-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3199 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/878/04878201.pdf [firstpage_image] =>[orig_patent_app_number] => 149269 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/149269
Semiconductor memory device having an improved timing signal generator for the column selection circuit Jan 27, 1988 Issued
Array ( [id] => 2533042 [patent_doc_number] => 04873671 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-10 [patent_title] => 'Sequential read access of serial memories with a user defined starting address' [patent_app_type] => 1 [patent_app_number] => 7/149399 [patent_app_country] => US [patent_app_date] => 1988-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2559 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/873/04873671.pdf [firstpage_image] =>[orig_patent_app_number] => 149399 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/149399
Sequential read access of serial memories with a user defined starting address Jan 27, 1988 Issued
Array ( [id] => 2531463 [patent_doc_number] => 04878198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Static ram with common data line equalization' [patent_app_type] => 1 [patent_app_number] => 7/148279 [patent_app_country] => US [patent_app_date] => 1988-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3383 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/878/04878198.pdf [firstpage_image] =>[orig_patent_app_number] => 148279 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/148279
Static ram with common data line equalization Jan 24, 1988 Issued
07/146999 HIGH DENSITY DATA STORAGE DEVICE AND METHOD USING ELECTRON TUNNELING TECHNIQUES Jan 21, 1988 Abandoned
Array ( [id] => 2484050 [patent_doc_number] => 04890262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-26 [patent_title] => 'Semiconductor memory with built-in defective bit relief circuit' [patent_app_type] => 1 [patent_app_number] => 7/142969 [patent_app_country] => US [patent_app_date] => 1988-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4531 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/890/04890262.pdf [firstpage_image] =>[orig_patent_app_number] => 142969 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/142969
Semiconductor memory with built-in defective bit relief circuit Jan 11, 1988 Issued
Array ( [id] => 2574412 [patent_doc_number] => 04858186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-15 [patent_title] => 'A circuit for providing a load for the charging of an EPROM cell' [patent_app_type] => 1 [patent_app_number] => 7/144569 [patent_app_country] => US [patent_app_date] => 1988-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2240 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/858/04858186.pdf [firstpage_image] =>[orig_patent_app_number] => 144569 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/144569
A circuit for providing a load for the charging of an EPROM cell Jan 11, 1988 Issued
Array ( [id] => 2486134 [patent_doc_number] => 04813022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-14 [patent_title] => 'Static memory with pull-up circuit for pulling-up a potential on a bit line' [patent_app_type] => 1 [patent_app_number] => 7/136769 [patent_app_country] => US [patent_app_date] => 1987-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3748 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/813/04813022.pdf [firstpage_image] =>[orig_patent_app_number] => 136769 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/136769
Static memory with pull-up circuit for pulling-up a potential on a bit line Dec 21, 1987 Issued
Array ( [id] => 2525061 [patent_doc_number] => 04875190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-17 [patent_title] => 'Two-dimensional memory unit having a 2d array of individually addressable blocks each having a 2d array of cells' [patent_app_type] => 1 [patent_app_number] => 7/135349 [patent_app_country] => US [patent_app_date] => 1987-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 9975 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/875/04875190.pdf [firstpage_image] =>[orig_patent_app_number] => 135349 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/135349
Two-dimensional memory unit having a 2d array of individually addressable blocks each having a 2d array of cells Dec 20, 1987 Issued
07/131589 SEMICONDUCTOR MEMORY DEVICE WITH CROSSED BIT LINE PAIRS Dec 10, 1987 Abandoned
Array ( [id] => 2499198 [patent_doc_number] => 04829483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-09 [patent_title] => 'Method and apparatus for selecting disconnecting first and second bit line pairs for sensing data output from a drain at a high speed' [patent_app_type] => 1 [patent_app_number] => 7/128779 [patent_app_country] => US [patent_app_date] => 1987-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 39 [patent_no_of_words] => 3608 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/829/04829483.pdf [firstpage_image] =>[orig_patent_app_number] => 128779 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/128779
Method and apparatus for selecting disconnecting first and second bit line pairs for sensing data output from a drain at a high speed Dec 3, 1987 Issued
Array ( [id] => 2498110 [patent_doc_number] => 04802129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-31 [patent_title] => 'RAM with dual precharge circuit and write recovery circuitry' [patent_app_type] => 1 [patent_app_number] => 7/128559 [patent_app_country] => US [patent_app_date] => 1987-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3611 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/802/04802129.pdf [firstpage_image] =>[orig_patent_app_number] => 128559 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/128559
RAM with dual precharge circuit and write recovery circuitry Dec 2, 1987 Issued
Array ( [id] => 2482874 [patent_doc_number] => 04879693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-07 [patent_title] => 'Device for the self-synchronization of the output circuits of a memory using a three-state gate' [patent_app_type] => 1 [patent_app_number] => 7/128169 [patent_app_country] => US [patent_app_date] => 1987-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3007 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/879/04879693.pdf [firstpage_image] =>[orig_patent_app_number] => 128169 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/128169
Device for the self-synchronization of the output circuits of a memory using a three-state gate Dec 2, 1987 Issued
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