| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_kind] => NA
[patent_issue_date] => 1990-08-28
[patent_title] => 'Semiconductor memory device having improved connecting structure of bit line and memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/173749
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[patent_app_date] => 1988-03-25
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Array
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[patent_doc_number] => 04804816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-02-14
[patent_title] => 'Method of making a thin-film magnetic head having a multi-layered coil structure'
[patent_app_type] => 1
[patent_app_number] => 7/165076
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[patent_app_date] => 1988-03-07
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[firstpage_image] =>[orig_patent_app_number] => 165076
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/165076 | Method of making a thin-film magnetic head having a multi-layered coil structure | Mar 6, 1988 | Issued |
Array
(
[id] => 2633528
[patent_doc_number] => 04956820
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-09-11
[patent_title] => 'Arbiter circuit for establishing priority control of read, write and refresh operations with respect to memory array'
[patent_app_type] => 1
[patent_app_number] => 7/161059
[patent_app_country] => US
[patent_app_date] => 1988-02-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/161059 | Arbiter circuit for establishing priority control of read, write and refresh operations with respect to memory array | Feb 25, 1988 | Issued |
Array
(
[id] => 2595478
[patent_doc_number] => 04926378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-05-15
[patent_title] => 'Bipolar static RAM having two wiring lines for each word line'
[patent_app_type] => 1
[patent_app_number] => 7/160259
[patent_app_country] => US
[patent_app_date] => 1988-02-25
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[firstpage_image] =>[orig_patent_app_number] => 160259
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/160259 | Bipolar static RAM having two wiring lines for each word line | Feb 24, 1988 | Issued |
Array
(
[id] => 2676892
[patent_doc_number] => 04935901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-06-19
[patent_title] => 'Semiconductor memory with divided bit load and data bus lines'
[patent_app_type] => 1
[patent_app_number] => 7/158259
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[patent_app_date] => 1988-02-19
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[firstpage_image] =>[orig_patent_app_number] => 158259
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/158259 | Semiconductor memory with divided bit load and data bus lines | Feb 18, 1988 | Issued |
| 07/152789 | ELECTRICALLY-ERASABLE, ELECTRICALLY-PROGRAMMABLE READ-ONLY MEMORY CELL | Feb 4, 1988 | Abandoned |
Array
(
[id] => 2420932
[patent_doc_number] => 04787006
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[patent_issue_date] => 1988-11-22
[patent_title] => 'Shutter pin groove for a magnetic disc cartridge'
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[patent_app_number] => 7/153497
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/153497 | Shutter pin groove for a magnetic disc cartridge | Feb 2, 1988 | Issued |
Array
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[id] => 2628634
[patent_doc_number] => 04894802
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[patent_issue_date] => 1990-01-16
[patent_title] => 'Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase'
[patent_app_type] => 1
[patent_app_number] => 7/151379
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[pdf_file] => patents/04/894/04894802.pdf
[firstpage_image] =>[orig_patent_app_number] => 151379
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/151379 | Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase | Feb 1, 1988 | Issued |
Array
(
[id] => 2531517
[patent_doc_number] => 04878201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-31
[patent_title] => 'Semiconductor memory device having an improved timing signal generator for the column selection circuit'
[patent_app_type] => 1
[patent_app_number] => 7/149269
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[patent_app_date] => 1988-01-28
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[firstpage_image] =>[orig_patent_app_number] => 149269
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/149269 | Semiconductor memory device having an improved timing signal generator for the column selection circuit | Jan 27, 1988 | Issued |
Array
(
[id] => 2533042
[patent_doc_number] => 04873671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-10
[patent_title] => 'Sequential read access of serial memories with a user defined starting address'
[patent_app_type] => 1
[patent_app_number] => 7/149399
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/149399 | Sequential read access of serial memories with a user defined starting address | Jan 27, 1988 | Issued |
Array
(
[id] => 2531463
[patent_doc_number] => 04878198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-31
[patent_title] => 'Static ram with common data line equalization'
[patent_app_type] => 1
[patent_app_number] => 7/148279
[patent_app_country] => US
[patent_app_date] => 1988-01-25
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[firstpage_image] =>[orig_patent_app_number] => 148279
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/148279 | Static ram with common data line equalization | Jan 24, 1988 | Issued |
| 07/146999 | HIGH DENSITY DATA STORAGE DEVICE AND METHOD USING ELECTRON TUNNELING TECHNIQUES | Jan 21, 1988 | Abandoned |
Array
(
[id] => 2484050
[patent_doc_number] => 04890262
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[patent_kind] => NA
[patent_issue_date] => 1989-12-26
[patent_title] => 'Semiconductor memory with built-in defective bit relief circuit'
[patent_app_type] => 1
[patent_app_number] => 7/142969
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[patent_app_date] => 1988-01-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/142969 | Semiconductor memory with built-in defective bit relief circuit | Jan 11, 1988 | Issued |
Array
(
[id] => 2574412
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[patent_kind] => NA
[patent_issue_date] => 1989-08-15
[patent_title] => 'A circuit for providing a load for the charging of an EPROM cell'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/144569 | A circuit for providing a load for the charging of an EPROM cell | Jan 11, 1988 | Issued |
Array
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[patent_issue_date] => 1989-03-14
[patent_title] => 'Static memory with pull-up circuit for pulling-up a potential on a bit line'
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Array
(
[id] => 2525061
[patent_doc_number] => 04875190
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1989-10-17
[patent_title] => 'Two-dimensional memory unit having a 2d array of individually addressable blocks each having a 2d array of cells'
[patent_app_type] => 1
[patent_app_number] => 7/135349
[patent_app_country] => US
[patent_app_date] => 1987-12-21
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[firstpage_image] =>[orig_patent_app_number] => 135349
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/135349 | Two-dimensional memory unit having a 2d array of individually addressable blocks each having a 2d array of cells | Dec 20, 1987 | Issued |
| 07/131589 | SEMICONDUCTOR MEMORY DEVICE WITH CROSSED BIT LINE PAIRS | Dec 10, 1987 | Abandoned |
Array
(
[id] => 2499198
[patent_doc_number] => 04829483
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[patent_kind] => NA
[patent_issue_date] => 1989-05-09
[patent_title] => 'Method and apparatus for selecting disconnecting first and second bit line pairs for sensing data output from a drain at a high speed'
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[patent_app_number] => 7/128779
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/128779 | Method and apparatus for selecting disconnecting first and second bit line pairs for sensing data output from a drain at a high speed | Dec 3, 1987 | Issued |
Array
(
[id] => 2498110
[patent_doc_number] => 04802129
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[patent_kind] => NA
[patent_issue_date] => 1989-01-31
[patent_title] => 'RAM with dual precharge circuit and write recovery circuitry'
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[firstpage_image] =>[orig_patent_app_number] => 128559
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/128559 | RAM with dual precharge circuit and write recovery circuitry | Dec 2, 1987 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1989-11-07
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[patent_app_number] => 7/128169
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/128169 | Device for the self-synchronization of the output circuits of a memory using a three-state gate | Dec 2, 1987 | Issued |