Search

John S Maples

Examiner (ID: 5405)

Most Active Art Unit
1745
Art Unit(s)
1104, 1754, 1795, 2203, 1741, 2201, 1111, 1107, 1723, 1745, 1728, 2202
Total Applications
2365
Issued Applications
1875
Pending Applications
115
Abandoned Applications
375

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19107623 [patent_doc_number] => 11960732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Method for identifying hard drive transitionally and finally with drive letter identification and electronic device [patent_app_type] => utility [patent_app_number] => 17/891543 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891543 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891543
Method for identifying hard drive transitionally and finally with drive letter identification and electronic device Aug 18, 2022 Issued
Array ( [id] => 18973798 [patent_doc_number] => 20240053890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => Data Storage Device That Detects And Releases Bottlenecks [patent_app_type] => utility [patent_app_number] => 17/885288 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885288
Data storage device that detects and releases bottlenecks Aug 9, 2022 Issued
Array ( [id] => 18933912 [patent_doc_number] => 11886340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-30 [patent_title] => Real-time processing in computer systems [patent_app_type] => utility [patent_app_number] => 17/818660 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818660
Real-time processing in computer systems Aug 8, 2022 Issued
Array ( [id] => 18196743 [patent_doc_number] => 20230050262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => HOST, OPERATING METHOD OF HOST AND STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/817714 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/817714
Host, operating method of host and storage system Aug 4, 2022 Issued
Array ( [id] => 18142571 [patent_doc_number] => 20230016415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => APPARATUS HAVING SELECTIVELY-ACTIVATED TERMINATION CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/851273 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851273
APPARATUS HAVING SELECTIVELY-ACTIVATED TERMINATION CIRCUITRY Jun 27, 2022 Pending
Array ( [id] => 19078106 [patent_doc_number] => 11947471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Unsuccessful write retry buffer [patent_app_type] => utility [patent_app_number] => 17/852135 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852135
Unsuccessful write retry buffer Jun 27, 2022 Issued
Array ( [id] => 18846839 [patent_doc_number] => 20230409243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => LOGICAL MEMORY ADDRESSING FOR NETWORK DEVICES [patent_app_type] => utility [patent_app_number] => 17/845740 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845740
Logical memory addressing for network devices Jun 20, 2022 Issued
Array ( [id] => 18912066 [patent_doc_number] => 11875045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Semiconductor memory and method for density configuring of bank of semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/844205 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11450 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844205
Semiconductor memory and method for density configuring of bank of semiconductor memory Jun 19, 2022 Issued
Array ( [id] => 17869286 [patent_doc_number] => 20220292023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => VICTIM CACHE WITH WRITE MISS MERGING [patent_app_type] => utility [patent_app_number] => 17/828189 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828189
Victim cache with write miss merging May 30, 2022 Issued
Array ( [id] => 18316695 [patent_doc_number] => 11630776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Methods and systems for fast allocation of fragmented caches [patent_app_type] => utility [patent_app_number] => 17/827209 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827209
Methods and systems for fast allocation of fragmented caches May 26, 2022 Issued
Array ( [id] => 19275972 [patent_doc_number] => 12026100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Method and system for low latency data management [patent_app_type] => utility [patent_app_number] => 17/825707 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825707
METHOD AND SYSTEM FOR LOW LATENCY DATA MANAGEMENT May 25, 2022 Pending
Array ( [id] => 17839658 [patent_doc_number] => 20220276963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => PREFETCH BUFFER OF MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/748726 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748726
Prefetch buffer of memory sub-system May 18, 2022 Issued
Array ( [id] => 19212275 [patent_doc_number] => 12001337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries [patent_app_type] => utility [patent_app_number] => 17/747749 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 39 [patent_no_of_words] => 41591 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747749
Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries May 17, 2022 Issued
Array ( [id] => 17992003 [patent_doc_number] => 20220358040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => UNFORWARDABLE LOAD INSTRUCTION RE-EXECUTION ELIGIBILITY BASED ON CACHE UPDATE BY IDENTIFIED STORE INSTRUCTION [patent_app_type] => utility [patent_app_number] => 17/747703 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 57913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747703
UNFORWARDABLE LOAD INSTRUCTION RE-EXECUTION ELIGIBILITY BASED ON CACHE UPDATE BY IDENTIFIED STORE INSTRUCTION May 17, 2022 Pending
Array ( [id] => 18741605 [patent_doc_number] => 20230350586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Flash-Translation-Layer-Aided Power Allocation in a Data Storage Device [patent_app_type] => utility [patent_app_number] => 17/734398 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734398
Flash-translation-layer-aided power allocation in a data storage device May 1, 2022 Issued
Array ( [id] => 17809515 [patent_doc_number] => 20220261350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Promoting Prefetched Data from a Cache Memory to Registers in a Processor [patent_app_type] => utility [patent_app_number] => 17/730754 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730754
Promoting Prefetched Data from a Cache Memory to Registers in a Processor Apr 26, 2022 Pending
Array ( [id] => 18291366 [patent_doc_number] => 11620236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Prefetch kill and revival in an instruction cache [patent_app_type] => utility [patent_app_number] => 17/727921 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727921
Prefetch kill and revival in an instruction cache Apr 24, 2022 Issued
Array ( [id] => 18622384 [patent_doc_number] => 11755425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Methods and systems for synchronous distributed data backup and metadata aggregation [patent_app_type] => utility [patent_app_number] => 17/722898 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722898
Methods and systems for synchronous distributed data backup and metadata aggregation Apr 17, 2022 Issued
Array ( [id] => 19092875 [patent_doc_number] => 11954329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Memory management method, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 17/721358 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7272 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721358
Memory management method, memory storage device and memory control circuit unit Apr 14, 2022 Issued
Array ( [id] => 17763289 [patent_doc_number] => 20220236901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Data Storage Method and Apparatus [patent_app_type] => utility [patent_app_number] => 17/720479 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720479
Data storage method and apparatus Apr 13, 2022 Issued
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