Search

John S Maples

Examiner (ID: 5405)

Most Active Art Unit
1745
Art Unit(s)
1104, 1754, 1795, 2203, 1741, 2201, 1111, 1107, 1723, 1745, 1728, 2202
Total Applications
2365
Issued Applications
1875
Pending Applications
115
Abandoned Applications
375

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16378219 [patent_doc_number] => 20200327061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => DATA PREFETCHING METHOD AND APPARATUS, AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/913680 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913680
Data prefetching method and apparatus, and storage device Jun 25, 2020 Issued
Array ( [id] => 16330884 [patent_doc_number] => 20200301850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => DATA PROCESSING METHOD AND NVME STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/899294 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/899294
Data processing method and NVMe storage device Jun 10, 2020 Issued
Array ( [id] => 16299854 [patent_doc_number] => 20200285577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => PREDICTIVE DATA STORAGE HIERARCHICAL MEMORY SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/884815 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16884815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/884815
Predictive data storage hierarchical memory systems and methods May 26, 2020 Issued
Array ( [id] => 17269302 [patent_doc_number] => 11194729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Victim cache that supports draining write-miss entries [patent_app_type] => utility [patent_app_number] => 16/882369 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 26305 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882369
Victim cache that supports draining write-miss entries May 21, 2020 Issued
Array ( [id] => 17907382 [patent_doc_number] => 11461236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Methods and apparatus for allocation in a victim cache system [patent_app_type] => utility [patent_app_number] => 16/882244 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 54 [patent_no_of_words] => 95337 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882244
Methods and apparatus for allocation in a victim cache system May 21, 2020 Issued
Array ( [id] => 16470388 [patent_doc_number] => 20200371925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => MERGING DATA FOR WRITE ALLOCATE [patent_app_type] => utility [patent_app_number] => 16/882356 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882356
Merging data for write allocate May 21, 2020 Issued
Array ( [id] => 16864394 [patent_doc_number] => 11023134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-01 [patent_title] => Addition of data services to an operating system running a native multi-path input-output architecture [patent_app_type] => utility [patent_app_number] => 16/881086 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 13433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881086 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/881086
Addition of data services to an operating system running a native multi-path input-output architecture May 21, 2020 Issued
Array ( [id] => 16470393 [patent_doc_number] => 20200371930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => HARDWARE COHERENCE FOR MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/882216 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882216
Hardware coherence for memory controller May 21, 2020 Issued
Array ( [id] => 17636925 [patent_doc_number] => 11347649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Victim cache with write miss merging [patent_app_type] => utility [patent_app_number] => 16/882403 [patent_app_country] => US [patent_app_date] => 2020-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 26297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882403 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882403
Victim cache with write miss merging May 21, 2020 Issued
Array ( [id] => 16810246 [patent_doc_number] => 20210132801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => OPTIMIZED ACCESS TO HIGH-SPEED STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/880271 [patent_app_country] => US [patent_app_date] => 2020-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/880271
Optimized access to high-speed storage device May 20, 2020 Issued
Array ( [id] => 17230697 [patent_doc_number] => 20210357254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => MULTI-PROCESSOR SYSTEM AND METHOD ENABLING CONCURRENT MULTI-PROCESSING UTILIZING DISCRETE COMPONENT PROCESSOR ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/875071 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16875071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/875071
MULTI-PROCESSOR SYSTEM AND METHOD ENABLING CONCURRENT MULTI-PROCESSING UTILIZING DISCRETE COMPONENT PROCESSOR ELEMENTS May 14, 2020 Abandoned
Array ( [id] => 17786548 [patent_doc_number] => 11409672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Unsuccessful write retry buffer [patent_app_type] => utility [patent_app_number] => 16/872681 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6449 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16872681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/872681
Unsuccessful write retry buffer May 11, 2020 Issued
Array ( [id] => 17106339 [patent_doc_number] => 11126556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => History table management for a correlated prefetcher [patent_app_type] => utility [patent_app_number] => 16/863284 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863284
History table management for a correlated prefetcher Apr 29, 2020 Issued
Array ( [id] => 17194943 [patent_doc_number] => 11163700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => Initiating interconnect operation without waiting on lower level cache directory lookup [patent_app_type] => utility [patent_app_number] => 16/862785 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862785 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/862785
Initiating interconnect operation without waiting on lower level cache directory lookup Apr 29, 2020 Issued
Array ( [id] => 17288152 [patent_doc_number] => 11204701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Token based transactions [patent_app_type] => utility [patent_app_number] => 16/826740 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826740
Token based transactions Mar 22, 2020 Issued
Array ( [id] => 16179012 [patent_doc_number] => 20200225980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => COMPUTING SYSTEMS AND METHODS OF OPERATING COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/826431 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826431
Computing systems and methods of operating computing systems Mar 22, 2020 Issued
Array ( [id] => 17325370 [patent_doc_number] => 11216382 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-04 [patent_title] => Intelligent hierarchical caching based on metrics for objects in different cache levels [patent_app_type] => utility [patent_app_number] => 16/820414 [patent_app_country] => US [patent_app_date] => 2020-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16820414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/820414
Intelligent hierarchical caching based on metrics for objects in different cache levels Mar 15, 2020 Issued
Array ( [id] => 17121921 [patent_doc_number] => 11133061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Disturb management based on write times [patent_app_type] => utility [patent_app_number] => 16/812559 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16812559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/812559
Disturb management based on write times Mar 8, 2020 Issued
Array ( [id] => 17084173 [patent_doc_number] => 20210279179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => I/O REQUEST TYPE SPECIFIC CACHE DIRECTORIES [patent_app_type] => utility [patent_app_number] => 16/808309 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808309
I/O request type specific cache directories Mar 2, 2020 Issued
Array ( [id] => 16957964 [patent_doc_number] => 11061828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Using multi-tiered cache to satisfy input/output requests [patent_app_type] => utility [patent_app_number] => 16/800889 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 20427 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800889 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/800889
Using multi-tiered cache to satisfy input/output requests Feb 24, 2020 Issued
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