John W. Poos

Array ( [id] => 10632167 [patent_doc_number] => 09350327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Flip-flops with low clock power' [patent_app_type] => utility [patent_app_number] => 14/498412 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11940 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10748061 [patent_doc_number] => 20160094212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Clock Monitoring for Sequential Logic Circuits' [patent_app_type] => utility [patent_app_number] => 14/497360 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4144 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11467490 [patent_doc_number] => 09584139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Phase tracker for a phase locked loop' [patent_app_type] => utility [patent_app_number] => 14/494718 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10674544 [patent_doc_number] => 20160020689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'CHARGE PUMP CIRCUIT AND PHASE LOCK LOOP CIRCUIT HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/490853 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6279 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10708230 [patent_doc_number] => 20160054377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'TESTING AND SETTING PERFORMANCE PARAMETERS IN A SEMICONDUCTOR DEVICE AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/484546 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10570815 [patent_doc_number] => 09294000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-22 [patent_title] => 'Direct conversion output driver' [patent_app_type] => utility [patent_app_number] => 14/484892 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3063 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10426891 [patent_doc_number] => 20150311902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'PLL WITH ACROSS-STAGE CONTROLLED DCO' [patent_app_type] => utility [patent_app_number] => 14/484779 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14484779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10508957 [patent_doc_number] => 09236834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Integrated circuit comprising fractional clock multiplication circuitry' [patent_app_type] => utility [patent_app_number] => 14/482782 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 5049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10726340 [patent_doc_number] => 20160072488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'VOLTAGE-DRIVER CIRCUIT WITH DYNAMIC SLEW RATE CONTROL' [patent_app_type] => utility [patent_app_number] => 14/480642 [patent_app_country] => US [patent_app_date] => 2014-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4757 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10378698 [patent_doc_number] => 20150263705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'SIGNAL TRANSMISSION CIRCUIT AND CLOCK BUFFER' [patent_app_type] => utility [patent_app_number] => 14/475502 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3728 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10461742 [patent_doc_number] => 20150346757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'ACTIVE DRIVER AND SEMICONDUCTOR DEVICE HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/475127 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4926 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10637158 [patent_doc_number] => 09354658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Method for asynchronous gating of signals between clock domains' [patent_app_type] => utility [patent_app_number] => 14/468982 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10564190 [patent_doc_number] => 09287873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Level shifter for a time-varying input' [patent_app_type] => utility [patent_app_number] => 14/463829 [patent_app_country] => US [patent_app_date] => 2014-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6988 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14463829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10703717 [patent_doc_number] => 20160049864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'POWER SUPPLYING CIRCUIT AND SOFT-START CIRCUIT OF THE SAME' [patent_app_type] => utility [patent_app_number] => 14/461135 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2478 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14461135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10930336 [patent_doc_number] => 20140333357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'CIRCUITS, APPARATUSES, AND METHODS FOR DELAY MODELS' [patent_app_type] => utility [patent_app_number] => 14/445924 [patent_app_country] => US [patent_app_date] => 2014-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5341 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14445924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10441206 [patent_doc_number] => 20150326218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'POWER-UP CIRCUIT OF SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/444396 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4743 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10682266 [patent_doc_number] => 20160028411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'FREQUENCY SYNTHESIZER WITH INJECTION PULLING/PUSHING SUPPRESSION/MITIGATION AND RELATED FREQUENCY SYNTHESIZING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/339459 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4580 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10531817 [patent_doc_number] => 09257966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Clock correction circuit and clock correction method' [patent_app_type] => utility [patent_app_number] => 14/340044 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 15148 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14340044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10190042 [patent_doc_number] => 09219474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Driver circuit for switching element' [patent_app_type] => utility [patent_app_number] => 14/331672 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10196413 [patent_doc_number] => 09225330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Level shifter including a timing control unit for high speed operation' [patent_app_type] => utility [patent_app_number] => 14/331009 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331009 [rel_patent_id] =>[rel_patent_doc_number] =>)