Search

John W. Poos

Examiner (ID: 7981, Phone: (571)270-5077 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2816, 2896, 2842, 4125
Total Applications
1592
Issued Applications
1425
Pending Applications
126
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9260328 [patent_doc_number] => 20130342257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'Multi-Point Analog to Single-Line Input for a PLC System' [patent_app_type] => utility [patent_app_number] => 13/921357 [patent_app_country] => US [patent_app_date] => 2013-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921357 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/921357
Multi-point analog to single-line input for a PLC system Jun 18, 2013 Issued
Array ( [id] => 9845221 [patent_doc_number] => 08947144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Apparatuses and methods for duty cycle adjustment' [patent_app_type] => utility [patent_app_number] => 13/920852 [patent_app_country] => US [patent_app_date] => 2013-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4352 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920852 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/920852
Apparatuses and methods for duty cycle adjustment Jun 17, 2013 Issued
Array ( [id] => 9255430 [patent_doc_number] => 08618853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Device including a clock generation circuit and a method of generating a clock signal' [patent_app_type] => utility [patent_app_number] => 13/918172 [patent_app_country] => US [patent_app_date] => 2013-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 5582 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/918172
Device including a clock generation circuit and a method of generating a clock signal Jun 13, 2013 Issued
Array ( [id] => 10832309 [patent_doc_number] => 08860486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/915552 [patent_app_country] => US [patent_app_date] => 2013-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3711 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13915552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/915552
Semiconductor device Jun 10, 2013 Issued
Array ( [id] => 9087151 [patent_doc_number] => 08558582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Low latency inter-die trigger serial interface for ADC' [patent_app_type] => utility [patent_app_number] => 13/915606 [patent_app_country] => US [patent_app_date] => 2013-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7955 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13915606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/915606
Low latency inter-die trigger serial interface for ADC Jun 10, 2013 Issued
Array ( [id] => 9750472 [patent_doc_number] => 08841954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Input signal processing device' [patent_app_type] => utility [patent_app_number] => 13/913655 [patent_app_country] => US [patent_app_date] => 2013-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6740 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13913655 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/913655
Input signal processing device Jun 9, 2013 Issued
Array ( [id] => 10054107 [patent_doc_number] => 09093995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Length-of-diffusion protected circuit and method of design' [patent_app_type] => utility [patent_app_number] => 13/905052 [patent_app_country] => US [patent_app_date] => 2013-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7078 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13905052 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/905052
Length-of-diffusion protected circuit and method of design May 28, 2013 Issued
Array ( [id] => 9663301 [patent_doc_number] => 08810291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Phase-locked loop' [patent_app_type] => utility [patent_app_number] => 13/900556 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3801 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900556
Phase-locked loop May 22, 2013 Issued
Array ( [id] => 9497503 [patent_doc_number] => 08736326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Frequency synthesizer and frequency synthesis method thereof' [patent_app_type] => utility [patent_app_number] => 13/900555 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4691 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900555 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900555
Frequency synthesizer and frequency synthesis method thereof May 22, 2013 Issued
Array ( [id] => 9763319 [patent_doc_number] => 08847650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-30 [patent_title] => 'Generating signal waveforms of a predetermined format' [patent_app_type] => utility [patent_app_number] => 13/898223 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3263 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898223 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/898223
Generating signal waveforms of a predetermined format May 19, 2013 Issued
Array ( [id] => 9145956 [patent_doc_number] => 20130300479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'METHOD AND DEVICE FOR GENERATING SHORT PULSES' [patent_app_type] => utility [patent_app_number] => 13/896566 [patent_app_country] => US [patent_app_date] => 2013-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13896566 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/896566
METHOD AND DEVICE FOR GENERATING SHORT PULSES May 16, 2013 Abandoned
Array ( [id] => 9159325 [patent_doc_number] => 20130307602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'DYNAMIC CLOCK PHASE CONTROL ARCHITECTURE FOR FREQUENCY SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 13/895849 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895849
Dynamic clock phase control architecture for frequency synthesis May 15, 2013 Issued
Array ( [id] => 9609172 [patent_doc_number] => 08786347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'Delay circuits for simulating delays based on a single cycle of a clock signal' [patent_app_type] => utility [patent_app_number] => 13/893703 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893703 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893703
Delay circuits for simulating delays based on a single cycle of a clock signal May 13, 2013 Issued
Array ( [id] => 9145940 [patent_doc_number] => 20130300463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Method and Apparatus for Monitoring Timing of Critical Paths' [patent_app_type] => utility [patent_app_number] => 13/891736 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6427 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891736 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891736
Method and apparatus for monitoring timing of critical paths May 9, 2013 Issued
Array ( [id] => 9039223 [patent_doc_number] => 20130241861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'PORTABLE ELECTRONIC DEVICE AND METHOD OF CONTROLLING SAME' [patent_app_type] => utility [patent_app_number] => 13/890435 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9586 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890435 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/890435
Portable electronic device and method of controlling same May 8, 2013 Issued
Array ( [id] => 10917172 [patent_doc_number] => 20140320191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'DIFFERENTIAL ANALOG SIGNAL PROCESSING STAGE WITH REDUCED EVEN ORDER HARMONIC DISTORTION' [patent_app_type] => utility [patent_app_number] => 13/874389 [patent_app_country] => US [patent_app_date] => 2013-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13874389 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/874389
Differential analog signal processing stage with reduced even order harmonic distortion Apr 29, 2013 Issued
Array ( [id] => 10260584 [patent_doc_number] => 20150145582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'PULSE GENERATING CIRCUIT FOR AUDIO-FREQUENCY AMPLIFIERS AND REGULATED POWER SUPPLIES' [patent_app_type] => utility [patent_app_number] => 14/397819 [patent_app_country] => US [patent_app_date] => 2013-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14397819 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/397819
Pulse generating circuit for audio-frequency amplifiers and regulated power supplies Apr 29, 2013 Issued
Array ( [id] => 9118785 [patent_doc_number] => 20130285707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'Wireless tachometer receiver' [patent_app_type] => utility [patent_app_number] => 13/872293 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872293 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872293
Wireless tachometer receiver Apr 28, 2013 Issued
Array ( [id] => 9145955 [patent_doc_number] => 20130300478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Method and Associated Apparatus for Clock-Data Edge Alignment' [patent_app_type] => utility [patent_app_number] => 13/872287 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5524 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872287 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872287
Method and associated apparatus for clock-data edge alignment Apr 28, 2013 Issued
Array ( [id] => 9032129 [patent_doc_number] => 20130234767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => '3D INTEGRATED CIRCUIT STACK-WIDE SYNCHRONIZATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/870279 [patent_app_country] => US [patent_app_date] => 2013-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5814 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13870279 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/870279
3D integrated circuit stack-wide synchronization circuit Apr 24, 2013 Issued
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