Search

John W Woolner

Examiner (ID: 13678)

Most Active Art Unit
2873
Art Unit(s)
2873
Total Applications
9
Issued Applications
8
Pending Applications
0
Abandoned Applications
1

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4457678 [patent_doc_number] => 07893518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Method for generating a layout, use of a transistor layout, and semiconductor circuit' [patent_app_type] => utility [patent_app_number] => 12/111181 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9064 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893518.pdf [firstpage_image] =>[orig_patent_app_number] => 12111181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111181
Method for generating a layout, use of a transistor layout, and semiconductor circuit Apr 27, 2008 Issued
Array ( [id] => 4836846 [patent_doc_number] => 20080277742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/110771 [patent_app_country] => US [patent_app_date] => 2008-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7375 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20080277742.pdf [firstpage_image] =>[orig_patent_app_number] => 12110771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110771
Semiconductor device Apr 27, 2008 Issued
Array ( [id] => 14711 [patent_doc_number] => 07804179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Plastic ball grid array ruggedization' [patent_app_type] => utility [patent_app_number] => 12/108792 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1601 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804179.pdf [firstpage_image] =>[orig_patent_app_number] => 12108792 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108792
Plastic ball grid array ruggedization Apr 23, 2008 Issued
Array ( [id] => 4856594 [patent_doc_number] => 20080265444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'THIN-FILM ALUMINUM NITRIDE ENCAPSULANT FOR METALLIC STRUCTURES ON INTEGRATED CIRCUITS AND METHOD OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 12/107181 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2425 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265444.pdf [firstpage_image] =>[orig_patent_app_number] => 12107181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107181
THIN-FILM ALUMINUM NITRIDE ENCAPSULANT FOR METALLIC STRUCTURES ON INTEGRATED CIRCUITS AND METHOD OF FORMING SAME Apr 21, 2008 Abandoned
Array ( [id] => 4883922 [patent_doc_number] => 20080258254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'PROCESS FOR REALIZING AN INTEGRATED ELECTRONIC CIRCUIT WITH TWO ACTIVE LAYER PORTIONS HAVING DIFFERENT CRYSTAL ORIENTATIONS' [patent_app_type] => utility [patent_app_number] => 12/104882 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4601 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20080258254.pdf [firstpage_image] =>[orig_patent_app_number] => 12104882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/104882
Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations Apr 16, 2008 Issued
Array ( [id] => 285874 [patent_doc_number] => 07550803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-23 [patent_title] => 'Vertical double-diffusion metal-oxide-semiconductor transistor device' [patent_app_type] => utility [patent_app_number] => 12/102871 [patent_app_country] => US [patent_app_date] => 2008-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2569 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/550/07550803.pdf [firstpage_image] =>[orig_patent_app_number] => 12102871 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/102871
Vertical double-diffusion metal-oxide-semiconductor transistor device Apr 14, 2008 Issued
Array ( [id] => 221384 [patent_doc_number] => 07608930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Semiconductor device and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/078772 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4860 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608930.pdf [firstpage_image] =>[orig_patent_app_number] => 12078772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078772
Semiconductor device and method of manufacturing semiconductor device Apr 3, 2008 Issued
Array ( [id] => 4488982 [patent_doc_number] => 07884428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/062072 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 55 [patent_no_of_words] => 10110 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884428.pdf [firstpage_image] =>[orig_patent_app_number] => 12062072 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062072
Semiconductor device and method for manufacturing the same Apr 2, 2008 Issued
Array ( [id] => 274209 [patent_doc_number] => 07560373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-14 [patent_title] => 'Low temperature solder metallurgy and process for packaging applications and structures formed thereby' [patent_app_type] => utility [patent_app_number] => 12/059281 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/560/07560373.pdf [firstpage_image] =>[orig_patent_app_number] => 12059281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/059281
Low temperature solder metallurgy and process for packaging applications and structures formed thereby Mar 30, 2008 Issued
Array ( [id] => 5469846 [patent_doc_number] => 20090243012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'ELECTROMAGNETIC INTERFERENCE SHIELD STRUCTURES FOR SEMICONDUCTOR COMPONENTS' [patent_app_type] => utility [patent_app_number] => 12/057762 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3763 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20090243012.pdf [firstpage_image] =>[orig_patent_app_number] => 12057762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/057762
ELECTROMAGNETIC INTERFERENCE SHIELD STRUCTURES FOR SEMICONDUCTOR COMPONENTS Mar 27, 2008 Abandoned
Array ( [id] => 168220 [patent_doc_number] => 07666757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method for manufacturing SOI substrate' [patent_app_type] => utility [patent_app_number] => 12/078211 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 80 [patent_no_of_words] => 22857 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/666/07666757.pdf [firstpage_image] =>[orig_patent_app_number] => 12078211 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078211
Method for manufacturing SOI substrate Mar 27, 2008 Issued
Array ( [id] => 5355126 [patent_doc_number] => 20090186470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/302372 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6310 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20090186470.pdf [firstpage_image] =>[orig_patent_app_number] => 12302372 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/302372
Method for manufacturing silicon carbide semiconductor element Mar 26, 2008 Issued
Array ( [id] => 4765179 [patent_doc_number] => 20080176390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'METHOD OF FORMING CARBON-CONTAINING SILICON NITRIDE LAYER' [patent_app_type] => utility [patent_app_number] => 12/055323 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3163 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20080176390.pdf [firstpage_image] =>[orig_patent_app_number] => 12055323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055323
METHOD OF FORMING CARBON-CONTAINING SILICON NITRIDE LAYER Mar 25, 2008 Abandoned
Array ( [id] => 185718 [patent_doc_number] => 07649257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Discrete placement of radiation sources on integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 12/051881 [patent_app_country] => US [patent_app_date] => 2008-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649257.pdf [firstpage_image] =>[orig_patent_app_number] => 12051881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051881
Discrete placement of radiation sources on integrated circuit devices Mar 19, 2008 Issued
Array ( [id] => 55024 [patent_doc_number] => 07768104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Apparatus and method for series connection of two die or chips in single electronics package' [patent_app_type] => utility [patent_app_number] => 12/050592 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6592 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/768/07768104.pdf [firstpage_image] =>[orig_patent_app_number] => 12050592 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050592
Apparatus and method for series connection of two die or chips in single electronics package Mar 17, 2008 Issued
Array ( [id] => 7589380 [patent_doc_number] => 07663190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'Tunable voltage isolation ground to ground ESD clamp' [patent_app_type] => utility [patent_app_number] => 12/049992 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3007 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663190.pdf [firstpage_image] =>[orig_patent_app_number] => 12049992 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/049992
Tunable voltage isolation ground to ground ESD clamp Mar 16, 2008 Issued
Array ( [id] => 4719528 [patent_doc_number] => 20080242051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/076147 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 20773 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242051.pdf [firstpage_image] =>[orig_patent_app_number] => 12076147 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076147
Method for manufacturing semiconductor device Mar 13, 2008 Issued
Array ( [id] => 4927510 [patent_doc_number] => 20080166873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/073274 [patent_app_country] => US [patent_app_date] => 2008-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5061 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20080166873.pdf [firstpage_image] =>[orig_patent_app_number] => 12073274 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073274
Method of manufacturing semiconductor device Mar 2, 2008 Issued
Array ( [id] => 5296641 [patent_doc_number] => 20090011567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Method for manufacturing display substrate' [patent_app_type] => utility [patent_app_number] => 12/073091 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2865 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20090011567.pdf [firstpage_image] =>[orig_patent_app_number] => 12073091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073091
Method for manufacturing display substrate Feb 28, 2008 Issued
Array ( [id] => 4782619 [patent_doc_number] => 20080135948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Device patterned with Sub-Lithographic Features with Variable Widths' [patent_app_type] => utility [patent_app_number] => 12/034972 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5640 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135948.pdf [firstpage_image] =>[orig_patent_app_number] => 12034972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034972
Device patterned with sub-lithographic features with variable widths Feb 20, 2008 Issued
Menu