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John W Woolner

Examiner (ID: 3746)

Most Active Art Unit
2873
Art Unit(s)
2873
Total Applications
9
Issued Applications
8
Pending Applications
0
Abandoned Applications
1

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1138450 [patent_doc_number] => 06780771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Forming a substantially planar upper surface at the outer edge of a semiconductor topography' [patent_app_type] => B1 [patent_app_number] => 09/768873 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 8093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780771.pdf [firstpage_image] =>[orig_patent_app_number] => 09768873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768873
Forming a substantially planar upper surface at the outer edge of a semiconductor topography Jan 22, 2001 Issued
Array ( [id] => 6895204 [patent_doc_number] => 20010025994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Process for producing semiconductor device and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/766613 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5052 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025994.pdf [firstpage_image] =>[orig_patent_app_number] => 09766613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766613
Process for producing semiconductor device and semiconductor device Jan 22, 2001 Abandoned
Array ( [id] => 6901523 [patent_doc_number] => 20010023106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Method for fabricating high voltage transistor' [patent_app_type] => new [patent_app_number] => 09/767264 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2857 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023106.pdf [firstpage_image] =>[orig_patent_app_number] => 09767264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767264
Method for fabricating high voltage transistor Jan 22, 2001 Issued
Array ( [id] => 6896221 [patent_doc_number] => 20010027011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment' [patent_app_type] => new [patent_app_number] => 09/765433 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6521 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027011.pdf [firstpage_image] =>[orig_patent_app_number] => 09765433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765433
Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity Jan 21, 2001 Issued
Array ( [id] => 6884933 [patent_doc_number] => 20010039095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Process for producing a bipolar transistor with self-aligned emitter and extrinsic base' [patent_app_type] => new [patent_app_number] => 09/766454 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2799 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039095.pdf [firstpage_image] =>[orig_patent_app_number] => 09766454 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766454
Process for producing a bipolar transistor with self-aligned emitter and extrinsic base Jan 18, 2001 Issued
Array ( [id] => 1261416 [patent_doc_number] => 06664144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method of forming a semiconductor device using a group XV element for gettering by means of infrared light' [patent_app_type] => B2 [patent_app_number] => 09/764432 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 26 [patent_no_of_words] => 6092 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664144.pdf [firstpage_image] =>[orig_patent_app_number] => 09764432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764432
Method of forming a semiconductor device using a group XV element for gettering by means of infrared light Jan 18, 2001 Issued
Array ( [id] => 5986449 [patent_doc_number] => 20020098673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Method for fabricating metal interconnects' [patent_app_type] => new [patent_app_number] => 09/886774 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098673.pdf [firstpage_image] =>[orig_patent_app_number] => 09886774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886774
Method for fabricating metal interconnects Jan 18, 2001 Abandoned
Array ( [id] => 1141697 [patent_doc_number] => 06777347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method to produce porous oxide including forming a precoating oxide and a thermal oxide' [patent_app_type] => B1 [patent_app_number] => 09/765044 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2208 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777347.pdf [firstpage_image] =>[orig_patent_app_number] => 09765044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765044
Method to produce porous oxide including forming a precoating oxide and a thermal oxide Jan 18, 2001 Issued
Array ( [id] => 6306734 [patent_doc_number] => 20020094649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Shallow trench isolation using non-conformal dielectric material and planarizatrion' [patent_app_type] => new [patent_app_number] => 09/764674 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2276 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094649.pdf [firstpage_image] =>[orig_patent_app_number] => 09764674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764674
Shallow trench isolation using non-conformal dielectric and planarizatrion Jan 17, 2001 Issued
Array ( [id] => 1352487 [patent_doc_number] => 06580176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation' [patent_app_type] => B2 [patent_app_number] => 09/760640 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 9975 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580176.pdf [firstpage_image] =>[orig_patent_app_number] => 09760640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760640
Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation Jan 16, 2001 Issued
Array ( [id] => 6896202 [patent_doc_number] => 20010026992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/761963 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9331 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026992.pdf [firstpage_image] =>[orig_patent_app_number] => 09761963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761963
Semiconductor device and method for manufacturing the same including forming a plurality of dummy convex regions on a matrix with a virtual linear line defining an angle Jan 16, 2001 Issued
Array ( [id] => 1458707 [patent_doc_number] => 06426247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Low bitline capacitance structure and method of making same' [patent_app_type] => B1 [patent_app_number] => 09/764824 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1752 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426247.pdf [firstpage_image] =>[orig_patent_app_number] => 09764824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764824
Low bitline capacitance structure and method of making same Jan 16, 2001 Issued
Array ( [id] => 7090932 [patent_doc_number] => 20010032995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors and methods of fabricating same' [patent_app_type] => new [patent_app_number] => 09/764253 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7222 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032995.pdf [firstpage_image] =>[orig_patent_app_number] => 09764253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764253
Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors Jan 16, 2001 Issued
Array ( [id] => 6306596 [patent_doc_number] => 20020094611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Low programming voltage anti-fuse structure' [patent_app_type] => new [patent_app_number] => 09/761294 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5053 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094611.pdf [firstpage_image] =>[orig_patent_app_number] => 09761294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761294
Low programming voltage anti-fuse structure Jan 15, 2001 Issued
Array ( [id] => 6651498 [patent_doc_number] => 20030008526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method of forming variable oxide thicknesses across semiconductor chips' [patent_app_type] => new [patent_app_number] => 09/760954 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1740 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008526.pdf [firstpage_image] =>[orig_patent_app_number] => 09760954 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760954
Method of forming variable oxide thicknesses across semiconductor chips Jan 15, 2001 Abandoned
Array ( [id] => 5847150 [patent_doc_number] => 20020133258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Nitrogen doping of FSG layer' [patent_app_type] => new [patent_app_number] => 09/759854 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8184 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133258.pdf [firstpage_image] =>[orig_patent_app_number] => 09759854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759854
Method of nitrogen doping of fluorinated silicate glass (FSG) while removing the photoresist layer Jan 11, 2001 Issued
Array ( [id] => 1367640 [patent_doc_number] => 06566248 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Graphoepitaxial conductor cores in integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/759114 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566248.pdf [firstpage_image] =>[orig_patent_app_number] => 09759114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759114
Graphoepitaxial conductor cores in integrated circuit interconnects Jan 10, 2001 Issued
Array ( [id] => 1594588 [patent_doc_number] => 06383920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Process of enclosing via for improved reliability in dual damascene interconnects' [patent_app_type] => B1 [patent_app_number] => 09/757894 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 8837 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383920.pdf [firstpage_image] =>[orig_patent_app_number] => 09757894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757894
Process of enclosing via for improved reliability in dual damascene interconnects Jan 9, 2001 Issued
Array ( [id] => 1025509 [patent_doc_number] => 06885064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Contact structure of wiring and a method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 09/755193 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/885/06885064.pdf [firstpage_image] =>[orig_patent_app_number] => 09755193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755193
Contact structure of wiring and a method for manufacturing the same Jan 7, 2001 Issued
Array ( [id] => 1389722 [patent_doc_number] => 06544834 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method of forming a semiconductor device including a capacitor with tantalum oxide (Ta2O5)' [patent_app_type] => B1 [patent_app_number] => 09/720002 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 47 [patent_no_of_words] => 15055 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544834.pdf [firstpage_image] =>[orig_patent_app_number] => 09720002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/720002
Method of forming a semiconductor device including a capacitor with tantalum oxide (Ta2O5) Dec 18, 2000 Issued
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