John W Woolner
Examiner (ID: 3746)
Most Active Art Unit | 2873 |
Art Unit(s) | 2873 |
Total Applications | 9 |
Issued Applications | 8 |
Pending Applications | 0 |
Abandoned Applications | 1 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1138450
[patent_doc_number] => 06780771
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[patent_issue_date] => 2004-08-24
[patent_title] => 'Forming a substantially planar upper surface at the outer edge of a semiconductor topography'
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[patent_app_number] => 09/768873
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[pdf_file] => patents/06/780/06780771.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768873 | Forming a substantially planar upper surface at the outer edge of a semiconductor topography | Jan 22, 2001 | Issued |
Array
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[patent_title] => 'Process for producing semiconductor device and semiconductor device'
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Array
(
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[patent_title] => 'Method for fabricating high voltage transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/767264 | Method for fabricating high voltage transistor | Jan 22, 2001 | Issued |
Array
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[patent_title] => 'Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment'
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Array
(
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Array
(
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[patent_title] => 'Method of forming a semiconductor device using a group XV element for gettering by means of infrared light'
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Array
(
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[patent_title] => 'Method for fabricating metal interconnects'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/886774 | Method for fabricating metal interconnects | Jan 18, 2001 | Abandoned |
Array
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[patent_issue_date] => 2004-08-17
[patent_title] => 'Method to produce porous oxide including forming a precoating oxide and a thermal oxide'
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[patent_app_number] => 09/765044
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Array
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[patent_title] => 'Shallow trench isolation using non-conformal dielectric material and planarizatrion'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/764674 | Shallow trench isolation using non-conformal dielectric and planarizatrion | Jan 17, 2001 | Issued |
Array
(
[id] => 1352487
[patent_doc_number] => 06580176
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[patent_kind] => B2
[patent_issue_date] => 2003-06-17
[patent_title] => 'Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation'
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[patent_app_number] => 09/760640
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Array
(
[id] => 6896202
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[patent_title] => 'Semiconductor device and method for manufacturing the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/761963 | Semiconductor device and method for manufacturing the same including forming a plurality of dummy convex regions on a matrix with a virtual linear line defining an angle | Jan 16, 2001 | Issued |
Array
(
[id] => 1458707
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Array
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Array
(
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[patent_title] => 'Low programming voltage anti-fuse structure'
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Array
(
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Array
(
[id] => 5847150
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[patent_issue_date] => 2002-09-19
[patent_title] => 'Nitrogen doping of FSG layer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/759854 | Method of nitrogen doping of fluorinated silicate glass (FSG) while removing the photoresist layer | Jan 11, 2001 | Issued |
Array
(
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[patent_title] => 'Graphoepitaxial conductor cores in integrated circuit interconnects'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/720002 | Method of forming a semiconductor device including a capacitor with tantalum oxide (Ta2O5) | Dec 18, 2000 | Issued |