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John W Woolner

Examiner (ID: 3746)

Most Active Art Unit
2873
Art Unit(s)
2873
Total Applications
9
Issued Applications
8
Pending Applications
0
Abandoned Applications
1

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6890125 [patent_doc_number] => 20010007356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-12 [patent_title] => 'Integrated circuit and fabricating method and evaluating method of integrated circuit' [patent_app_type] => new-utility [patent_app_number] => 09/734742 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5709 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20010007356.pdf [firstpage_image] =>[orig_patent_app_number] => 09734742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734742
Integrated circuit and fabricating method and evaluating method of integrated circuit Dec 12, 2000 Issued
Array ( [id] => 7634314 [patent_doc_number] => 06657306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/722467 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 8604 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657306.pdf [firstpage_image] =>[orig_patent_app_number] => 09722467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722467
Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method Nov 27, 2000 Issued
Array ( [id] => 1494742 [patent_doc_number] => 06403392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for patterning devices' [patent_app_type] => B1 [patent_app_number] => 09/723287 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403392.pdf [firstpage_image] =>[orig_patent_app_number] => 09723287 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723287
Method for patterning devices Nov 27, 2000 Issued
Array ( [id] => 1544191 [patent_doc_number] => 06373080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Thin film transistor with electrode on one side of a trench' [patent_app_type] => B1 [patent_app_number] => 09/717126 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1999 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373080.pdf [firstpage_image] =>[orig_patent_app_number] => 09717126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717126
Thin film transistor with electrode on one side of a trench Nov 21, 2000 Issued
Array ( [id] => 1441026 [patent_doc_number] => 06495897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Integrated circuit having etch-resistant layer substantially covering shallow trench regions' [patent_app_type] => B1 [patent_app_number] => 09/691932 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2306 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495897.pdf [firstpage_image] =>[orig_patent_app_number] => 09691932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691932
Integrated circuit having etch-resistant layer substantially covering shallow trench regions Oct 18, 2000 Issued
Array ( [id] => 1561763 [patent_doc_number] => 06437406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Super-halo formation in FETs' [patent_app_type] => B1 [patent_app_number] => 09/692093 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2097 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437406.pdf [firstpage_image] =>[orig_patent_app_number] => 09692093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/692093
Super-halo formation in FETs Oct 18, 2000 Issued
Array ( [id] => 1126502 [patent_doc_number] => 06790718 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method of manufacturing semiconductor memory device including one step of forming exposing the surface of the select transistors while not exposing the surface cell transistors' [patent_app_type] => B1 [patent_app_number] => 09/688203 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 4928 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790718.pdf [firstpage_image] =>[orig_patent_app_number] => 09688203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688203
Method of manufacturing semiconductor memory device including one step of forming exposing the surface of the select transistors while not exposing the surface cell transistors Oct 15, 2000 Issued
Array ( [id] => 1463747 [patent_doc_number] => 06351037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/672763 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4337 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351037.pdf [firstpage_image] =>[orig_patent_app_number] => 09672763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672763
Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits Sep 28, 2000 Issued
Array ( [id] => 1306564 [patent_doc_number] => 06617207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method and system for forming a stacked gate insulating film' [patent_app_type] => B1 [patent_app_number] => 09/662593 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8160 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617207.pdf [firstpage_image] =>[orig_patent_app_number] => 09662593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662593
Method and system for forming a stacked gate insulating film Sep 13, 2000 Issued
Array ( [id] => 1115533 [patent_doc_number] => 06800512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Method of forming insulating film and method of fabricating semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/662004 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 71 [patent_no_of_words] => 16214 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800512.pdf [firstpage_image] =>[orig_patent_app_number] => 09662004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662004
Method of forming insulating film and method of fabricating semiconductor device Sep 13, 2000 Issued
Array ( [id] => 1517281 [patent_doc_number] => 06500731 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Process for producing semiconductor device module' [patent_app_type] => B1 [patent_app_number] => 09/662604 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3622 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500731.pdf [firstpage_image] =>[orig_patent_app_number] => 09662604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662604
Process for producing semiconductor device module Sep 13, 2000 Issued
Array ( [id] => 7631368 [patent_doc_number] => 06635564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Semiconductor structure and method of fabrication including forming aluminum columns' [patent_app_type] => B1 [patent_app_number] => 09/662424 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2756 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635564.pdf [firstpage_image] =>[orig_patent_app_number] => 09662424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662424
Semiconductor structure and method of fabrication including forming aluminum columns Sep 13, 2000 Issued
Array ( [id] => 1371561 [patent_doc_number] => 06562683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Bit-line oxidation by removing ONO oxide prior to bit-line implant' [patent_app_type] => B1 [patent_app_number] => 09/651704 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2164 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562683.pdf [firstpage_image] =>[orig_patent_app_number] => 09651704 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651704
Bit-line oxidation by removing ONO oxide prior to bit-line implant Aug 30, 2000 Issued
Array ( [id] => 1285152 [patent_doc_number] => 06638831 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Use of a reference fiducial on a semiconductor package to monitor and control a singulation method' [patent_app_type] => B1 [patent_app_number] => 09/653473 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5054 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638831.pdf [firstpage_image] =>[orig_patent_app_number] => 09653473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653473
Use of a reference fiducial on a semiconductor package to monitor and control a singulation method Aug 30, 2000 Issued
Array ( [id] => 1520725 [patent_doc_number] => 06413852 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material' [patent_app_type] => B1 [patent_app_number] => 09/652754 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 31 [patent_no_of_words] => 5452 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413852.pdf [firstpage_image] =>[orig_patent_app_number] => 09652754 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652754
Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material Aug 30, 2000 Issued
Array ( [id] => 1549873 [patent_doc_number] => 06346484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method for selective extraction of sacrificial place-holding material used in fabrication of air gap-containing interconnect structures' [patent_app_type] => B1 [patent_app_number] => 09/651843 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346484.pdf [firstpage_image] =>[orig_patent_app_number] => 09651843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651843
Method for selective extraction of sacrificial place-holding material used in fabrication of air gap-containing interconnect structures Aug 30, 2000 Issued
Array ( [id] => 1514455 [patent_doc_number] => 06420213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive' [patent_app_type] => B1 [patent_app_number] => 09/653334 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8788 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420213.pdf [firstpage_image] =>[orig_patent_app_number] => 09653334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653334
Method for fixing a semiconductor device having stud bumps to a substrate by an electrically non-conductive adhesive Aug 30, 2000 Issued
Array ( [id] => 1073654 [patent_doc_number] => 06838319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically' [patent_app_type] => utility [patent_app_number] => 09/652503 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4101 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838319.pdf [firstpage_image] =>[orig_patent_app_number] => 09652503 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652503
Transfer molding and underfilling method and apparatus including orienting the active surface of a semiconductor substrate substantially vertically Aug 30, 2000 Issued
Array ( [id] => 1248197 [patent_doc_number] => 06673670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method of forming a capacitor structure and DRAM circuitry having a capacitor structure including interior areas spaced apart from one another in a non-overlapping relationship' [patent_app_type] => B1 [patent_app_number] => 09/653152 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2048 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673670.pdf [firstpage_image] =>[orig_patent_app_number] => 09653152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653152
Method of forming a capacitor structure and DRAM circuitry having a capacitor structure including interior areas spaced apart from one another in a non-overlapping relationship Aug 30, 2000 Issued
Array ( [id] => 1485046 [patent_doc_number] => 06365419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'High density MRAM cell array' [patent_app_type] => B1 [patent_app_number] => 09/649114 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2993 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365419.pdf [firstpage_image] =>[orig_patent_app_number] => 09649114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649114
High density MRAM cell array Aug 27, 2000 Issued
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