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John W Woolner

Examiner (ID: 3746)

Most Active Art Unit
2873
Art Unit(s)
2873
Total Applications
9
Issued Applications
8
Pending Applications
0
Abandoned Applications
1

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4349882 [patent_doc_number] => 06291265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method of manufacturing an interposer' [patent_app_type] => 1 [patent_app_number] => 9/501034 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4214 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291265.pdf [firstpage_image] =>[orig_patent_app_number] => 501034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501034
Method of manufacturing an interposer Feb 8, 2000 Issued
Array ( [id] => 4381732 [patent_doc_number] => 06261943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for fabricating free-standing thin metal films' [patent_app_type] => 1 [patent_app_number] => 9/499983 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 4850 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261943.pdf [firstpage_image] =>[orig_patent_app_number] => 499983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499983
Method for fabricating free-standing thin metal films Feb 7, 2000 Issued
Array ( [id] => 4266907 [patent_doc_number] => 06306720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for forming capacitor of mixed-mode device' [patent_app_type] => 1 [patent_app_number] => 9/492563 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1896 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306720.pdf [firstpage_image] =>[orig_patent_app_number] => 492563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492563
Method for forming capacitor of mixed-mode device Jan 26, 2000 Issued
Array ( [id] => 4407801 [patent_doc_number] => 06265230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Methods to cure the effects of hydrogen annealing on ferroelectric capacitors' [patent_app_type] => 1 [patent_app_number] => 9/488023 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7557 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265230.pdf [firstpage_image] =>[orig_patent_app_number] => 488023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488023
Methods to cure the effects of hydrogen annealing on ferroelectric capacitors Jan 19, 2000 Issued
Array ( [id] => 4301783 [patent_doc_number] => 06251725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of fabricating a DRAM storage node on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/479934 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 2868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251725.pdf [firstpage_image] =>[orig_patent_app_number] => 479934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479934
Method of fabricating a DRAM storage node on a semiconductor wafer Jan 9, 2000 Issued
Array ( [id] => 1520667 [patent_doc_number] => 06413823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Methods of forming field effect transistors' [patent_app_type] => B1 [patent_app_number] => 09/460253 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3382 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413823.pdf [firstpage_image] =>[orig_patent_app_number] => 09460253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460253
Methods of forming field effect transistors Dec 12, 1999 Issued
Array ( [id] => 4289561 [patent_doc_number] => 06235579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method for manufacturing stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 9/451384 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3184 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235579.pdf [firstpage_image] =>[orig_patent_app_number] => 451384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/451384
Method for manufacturing stacked capacitor Nov 29, 1999 Issued
Array ( [id] => 1414532 [patent_doc_number] => 06521514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates' [patent_app_type] => B1 [patent_app_number] => 09/441753 [patent_app_country] => US [patent_app_date] => 1999-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5617 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521514.pdf [firstpage_image] =>[orig_patent_app_number] => 09441753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/441753
Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates Nov 16, 1999 Issued
Array ( [id] => 7645716 [patent_doc_number] => 06472253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Programmable semiconductor device structures and methods for making the same' [patent_app_type] => B1 [patent_app_number] => 09/440103 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5112 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472253.pdf [firstpage_image] =>[orig_patent_app_number] => 09440103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440103
Programmable semiconductor device structures and methods for making the same Nov 14, 1999 Issued
Array ( [id] => 1588929 [patent_doc_number] => 06482735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method for improved metal fill by treatment of mobility layers' [patent_app_type] => B1 [patent_app_number] => 09/428159 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5188 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482735.pdf [firstpage_image] =>[orig_patent_app_number] => 09428159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428159
Method for improved metal fill by treatment of mobility layers Oct 26, 1999 Issued
Array ( [id] => 4301364 [patent_doc_number] => 06251696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate' [patent_app_type] => 1 [patent_app_number] => 9/426184 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 5823 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251696.pdf [firstpage_image] =>[orig_patent_app_number] => 426184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426184
Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate Oct 24, 1999 Issued
Array ( [id] => 4344434 [patent_doc_number] => 06284630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for fabrication of abrupt drain and source extensions for a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 9/421304 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3906 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284630.pdf [firstpage_image] =>[orig_patent_app_number] => 421304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421304
Method for fabrication of abrupt drain and source extensions for a field effect transistor Oct 19, 1999 Issued
Array ( [id] => 1440118 [patent_doc_number] => 06495456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method of manufacturing chip type electronic parts' [patent_app_type] => B1 [patent_app_number] => 09/416294 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4758 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495456.pdf [firstpage_image] =>[orig_patent_app_number] => 09416294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416294
Method of manufacturing chip type electronic parts Oct 13, 1999 Issued
Array ( [id] => 4343666 [patent_doc_number] => 06284579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications' [patent_app_type] => 1 [patent_app_number] => 9/418034 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2872 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284579.pdf [firstpage_image] =>[orig_patent_app_number] => 418034 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418034
Drain leakage reduction by indium transient enchanced diffusion (TED) for low power applications Oct 13, 1999 Issued
Array ( [id] => 1478091 [patent_doc_number] => 06451661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'DRAM capacitor formulation using a double-sided electrode' [patent_app_type] => B1 [patent_app_number] => 09/415213 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 4443 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451661.pdf [firstpage_image] =>[orig_patent_app_number] => 09415213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415213
DRAM capacitor formulation using a double-sided electrode Oct 11, 1999 Issued
Array ( [id] => 4408569 [patent_doc_number] => 06300221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method of fabricating nanoscale structures' [patent_app_type] => 1 [patent_app_number] => 9/409164 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3418 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300221.pdf [firstpage_image] =>[orig_patent_app_number] => 409164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409164
Method of fabricating nanoscale structures Sep 29, 1999 Issued
Array ( [id] => 4247035 [patent_doc_number] => 06221727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology' [patent_app_type] => 1 [patent_app_number] => 9/385524 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1675 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221727.pdf [firstpage_image] =>[orig_patent_app_number] => 385524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385524
Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technology Aug 29, 1999 Issued
Array ( [id] => 4326489 [patent_doc_number] => 06319764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of forming haze-free BST films' [patent_app_type] => 1 [patent_app_number] => 9/382753 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319764.pdf [firstpage_image] =>[orig_patent_app_number] => 382753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382753
Method of forming haze-free BST films Aug 24, 1999 Issued
Array ( [id] => 1390259 [patent_doc_number] => 06531036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Fabrication of micron-sized parts from conductive materials by silicon electric-discharge machining' [patent_app_type] => B1 [patent_app_number] => 09/383113 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 6143 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531036.pdf [firstpage_image] =>[orig_patent_app_number] => 09383113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383113
Fabrication of micron-sized parts from conductive materials by silicon electric-discharge machining Aug 24, 1999 Issued
Array ( [id] => 4408406 [patent_doc_number] => 06228690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of manufacturing fuse element used in memory device and fuse element' [patent_app_type] => 1 [patent_app_number] => 9/382514 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5321 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228690.pdf [firstpage_image] =>[orig_patent_app_number] => 382514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382514
Method of manufacturing fuse element used in memory device and fuse element Aug 24, 1999 Issued
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