John W Woolner

Array ( [id] => 4420367 [patent_doc_number] => 06225193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of cleaving a semiconductor wafer including implanting and annealing resulting in exfoliation' [patent_app_type] => 1 [patent_app_number] => 9/377054 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4717 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225193.pdf [firstpage_image] =>[orig_patent_app_number] => 377054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407545 [patent_doc_number] => 06239014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Tungsten bit line structure featuring a sandwich capping layer' [patent_app_type] => 1 [patent_app_number] => 9/374313 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2530 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239014.pdf [firstpage_image] =>[orig_patent_app_number] => 374313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258188 [patent_doc_number] => 06204118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for fabrication an open can-type stacked capacitor on local topology' [patent_app_type] => 1 [patent_app_number] => 9/373214 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204118.pdf [firstpage_image] =>[orig_patent_app_number] => 373214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350267 [patent_doc_number] => 06291293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for fabricating an open can-type stacked capacitor on an uneven surface' [patent_app_type] => 1 [patent_app_number] => 9/373484 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4753 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291293.pdf [firstpage_image] =>[orig_patent_app_number] => 373484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361921 [patent_doc_number] => 06569756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/361984 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 4276 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569756.pdf [firstpage_image] =>[orig_patent_app_number] => 09361984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6081105 [patent_doc_number] => 20020081800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'ELECTRODE, SEMICONDUCTOR DEVICE AND METHODS FOR MAKING THEM' [patent_app_type] => new [patent_app_number] => 09/360624 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8747 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 38 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081800.pdf [firstpage_image] =>[orig_patent_app_number] => 09360624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404892 [patent_doc_number] => 06271101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Process for production of SOI substrate and process for production of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/356704 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 25 [patent_no_of_words] => 4575 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271101.pdf [firstpage_image] =>[orig_patent_app_number] => 356704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302890 [patent_doc_number] => 06251799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method to provide low dielectric constant voids between adjacent conducting lines in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/356004 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251799.pdf [firstpage_image] =>[orig_patent_app_number] => 356004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561042 [patent_doc_number] => 06362027 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Semiconductor device, active matrix substrate, method of manufacturing the semiconductor device and method of manufacturing the active matrix substrate' [patent_app_type] => B1 [patent_app_number] => 09/348617 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 142 [patent_no_of_words] => 31705 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362027.pdf [firstpage_image] =>[orig_patent_app_number] => 09348617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7028164 [patent_doc_number] => 20010014507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'METHOD OF FORMING A DUAL LOCAL OXIDATION STRUCTURE OF A MEMORY CHIP IN A SEMICONDUCTOR WAFER' [patent_app_type] => new [patent_app_number] => 09/345814 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2470 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014507.pdf [firstpage_image] =>[orig_patent_app_number] => 09345814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407181 [patent_doc_number] => 06238980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for manufacturing silicon carbide MOS semiconductor device including utilizing difference in mask edges in implanting' [patent_app_type] => 1 [patent_app_number] => 9/343843 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 7348 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238980.pdf [firstpage_image] =>[orig_patent_app_number] => 343843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407055 [patent_doc_number] => 06238970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for fabricating a DRAM cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern' [patent_app_type] => 1 [patent_app_number] => 9/343353 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2438 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238970.pdf [firstpage_image] =>[orig_patent_app_number] => 343353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495050 [patent_doc_number] => 06403472 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contacts' [patent_app_type] => B1 [patent_app_number] => 09/339274 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1003 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403472.pdf [firstpage_image] =>[orig_patent_app_number] => 09339274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380801 [patent_doc_number] => 06294401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Nanoparticle-based electrical, chemical, and mechanical structures and methods of making same' [patent_app_type] => 1 [patent_app_number] => 9/334873 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4051 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294401.pdf [firstpage_image] =>[orig_patent_app_number] => 334873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303578 [patent_doc_number] => 06326253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for fabricating semiconductor device including MIS and bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 9/333050 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 6539 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326253.pdf [firstpage_image] =>[orig_patent_app_number] => 333050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1458735 [patent_doc_number] => 06426254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method for expanding trenches by an anisotropic wet etch' [patent_app_type] => B2 [patent_app_number] => 09/328763 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4253 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426254.pdf [firstpage_image] =>[orig_patent_app_number] => 09328763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151861 [patent_doc_number] => 06124158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of reducing carbon contamination of a thin dielectric film by using gaseous organic precursors, inert gas, and ozone to react with carbon contaminants' [patent_app_type] => 1 [patent_app_number] => 9/327793 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3848 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124158.pdf [firstpage_image] =>[orig_patent_app_number] => 327793 [rel_patent_id] =>[rel_patent_doc_number] =>)