Search

John Zazworsky

Examiner (ID: 6934)

Most Active Art Unit
2504
Art Unit(s)
2504, 2107, 2607
Total Applications
1204
Issued Applications
1067
Pending Applications
0
Abandoned Applications
137

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1180388 [patent_doc_number] => 06744115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Semiconductor device and process of production of same' [patent_app_type] => B2 [patent_app_number] => 09/899331 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 55 [patent_no_of_words] => 13599 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744115.pdf [firstpage_image] =>[orig_patent_app_number] => 09899331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899331
Semiconductor device and process of production of same Jul 4, 2001 Issued
Array ( [id] => 954107 [patent_doc_number] => 06958522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Method to fabricate passive components using conductive polymer' [patent_app_type] => utility [patent_app_number] => 09/897891 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2291 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958522.pdf [firstpage_image] =>[orig_patent_app_number] => 09897891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897891
Method to fabricate passive components using conductive polymer Jul 4, 2001 Issued
Array ( [id] => 1391111 [patent_doc_number] => 06552392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'MOS integrated circuit with reduced ON resistance' [patent_app_type] => B2 [patent_app_number] => 09/899332 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5732 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552392.pdf [firstpage_image] =>[orig_patent_app_number] => 09899332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899332
MOS integrated circuit with reduced ON resistance Jul 2, 2001 Issued
Array ( [id] => 6755843 [patent_doc_number] => 20030003620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Semiconductor device and manufacturing method of the same' [patent_app_type] => new [patent_app_number] => 09/895301 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5424 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003620.pdf [firstpage_image] =>[orig_patent_app_number] => 09895301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895301
Semiconductor device and manufacturing method of the same Jul 1, 2001 Issued
Array ( [id] => 7639821 [patent_doc_number] => 06396095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor memory and method of driving semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/869522 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4256 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396095.pdf [firstpage_image] =>[orig_patent_app_number] => 09869522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/869522
Semiconductor memory and method of driving semiconductor memory Jun 28, 2001 Issued
Array ( [id] => 6137925 [patent_doc_number] => 20020000634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Connection element' [patent_app_type] => new [patent_app_number] => 09/888020 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2764 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000634.pdf [firstpage_image] =>[orig_patent_app_number] => 09888020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888020
Connection element Jun 21, 2001 Abandoned
09/885462 Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base Jun 19, 2001 Abandoned
Array ( [id] => 1379568 [patent_doc_number] => 06563153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Electrically tunable device and a method relating thereto' [patent_app_type] => B2 [patent_app_number] => 09/885520 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6788 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563153.pdf [firstpage_image] =>[orig_patent_app_number] => 09885520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885520
Electrically tunable device and a method relating thereto Jun 19, 2001 Issued
Array ( [id] => 6494411 [patent_doc_number] => 20020190343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => ' Integration of two memory types on the same integrated circuit' [patent_app_type] => new [patent_app_number] => 09/881332 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190343.pdf [firstpage_image] =>[orig_patent_app_number] => 09881332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881332
Integration of two memory types on the same integrated circuit Jun 14, 2001 Issued
Array ( [id] => 6494416 [patent_doc_number] => 20020190344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Semiconductor device having a ghost source/drain region and a method of manufacture therefor' [patent_app_type] => new [patent_app_number] => 09/882911 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190344.pdf [firstpage_image] =>[orig_patent_app_number] => 09882911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882911
Semiconductor device having a ghost source/drain region and a method of manufacture therefor Jun 14, 2001 Issued
Array ( [id] => 1249124 [patent_doc_number] => 06674147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Semiconductor device having a bipolar transistor structure' [patent_app_type] => B2 [patent_app_number] => 09/873412 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 6572 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674147.pdf [firstpage_image] =>[orig_patent_app_number] => 09873412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873412
Semiconductor device having a bipolar transistor structure Jun 4, 2001 Issued
Array ( [id] => 6137744 [patent_doc_number] => 20020000586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Capacitively coupled ferroelectric random access memory cell and a method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/873772 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2616 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000586.pdf [firstpage_image] =>[orig_patent_app_number] => 09873772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873772
Capacitively coupled ferroelectric random access memory cell and a method for manufacturing the same Jun 3, 2001 Issued
Array ( [id] => 1022505 [patent_doc_number] => 06888198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Straddled gate FDSOI device' [patent_app_type] => utility [patent_app_number] => 09/873674 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6080 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888198.pdf [firstpage_image] =>[orig_patent_app_number] => 09873674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873674
Straddled gate FDSOI device Jun 3, 2001 Issued
Array ( [id] => 1480543 [patent_doc_number] => 06452236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Channel implant for improving NMOS ESD robustness' [patent_app_type] => B1 [patent_app_number] => 09/870901 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4720 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452236.pdf [firstpage_image] =>[orig_patent_app_number] => 09870901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870901
Channel implant for improving NMOS ESD robustness May 30, 2001 Issued
Array ( [id] => 6881672 [patent_doc_number] => 20010048144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Compensation component and process for producing the compensation component' [patent_app_type] => new [patent_app_number] => 09/867502 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2824 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048144.pdf [firstpage_image] =>[orig_patent_app_number] => 09867502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867502
Compensation component and process for producing the compensation component May 29, 2001 Issued
Array ( [id] => 7076931 [patent_doc_number] => 20010040273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/851441 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6139 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040273.pdf [firstpage_image] =>[orig_patent_app_number] => 09851441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851441
Semiconductor device with FET MESA structure and vertical contact electrodes May 7, 2001 Issued
Array ( [id] => 6348805 [patent_doc_number] => 20020056859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Field effect transistor with reduced gate delay and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 09/847622 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4677 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056859.pdf [firstpage_image] =>[orig_patent_app_number] => 09847622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847622
Field effect transistor with reduced gate delay and method of fabricating the same May 1, 2001 Issued
Array ( [id] => 7963817 [patent_doc_number] => 06680519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry' [patent_app_type] => B2 [patent_app_number] => 09/844059 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2129 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680519.pdf [firstpage_image] =>[orig_patent_app_number] => 09844059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844059
Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry Apr 25, 2001 Issued
09/486223 Ferroelectric device and semiconductor device Apr 23, 2001 Abandoned
Array ( [id] => 1309844 [patent_doc_number] => 06617623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Multi-layered gate for a CMOS imager' [patent_app_type] => B2 [patent_app_number] => 09/832856 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617623.pdf [firstpage_image] =>[orig_patent_app_number] => 09832856 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832856
Multi-layered gate for a CMOS imager Apr 11, 2001 Issued
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