John Zazworsky

Array ( [id] => 1441024 [patent_doc_number] => 06495896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Semiconductor integrated circuit device with high and low voltage wells' [patent_app_type] => B1 [patent_app_number] => 09/407401 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 96 [patent_figures_cnt] => 376 [patent_no_of_words] => 31586 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495896.pdf [firstpage_image] =>[orig_patent_app_number] => 09407401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4360332 [patent_doc_number] => 06218686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Charge coupled devices' [patent_app_type] => 1 [patent_app_number] => 9/405492 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3744 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218686.pdf [firstpage_image] =>[orig_patent_app_number] => 405492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4276707 [patent_doc_number] => 06246071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Zirconia-containing transparent and conducting oxides' [patent_app_type] => 1 [patent_app_number] => 9/404722 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3527 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246071.pdf [firstpage_image] =>[orig_patent_app_number] => 404722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7639807 [patent_doc_number] => 06396109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Isolated NMOS transistor fabricated in a digital BiCMOS process' [patent_app_type] => B1 [patent_app_number] => 09/388943 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2734 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396109.pdf [firstpage_image] =>[orig_patent_app_number] => 09388943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619793 [patent_doc_number] => 06943392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen' [patent_app_type] => utility [patent_app_number] => 09/388063 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2767 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943392.pdf [firstpage_image] =>[orig_patent_app_number] => 09388063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1566267 [patent_doc_number] => 06339245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Nitride overhang structure for the silicidation of transistor electrodes with shallow junctions' [patent_app_type] => B1 [patent_app_number] => 09/378653 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 5569 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339245.pdf [firstpage_image] =>[orig_patent_app_number] => 09378653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587735 [patent_doc_number] => 06359293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Integrated optoelectronic device with an avalanche photodetector and method of making the same using commercial CMOS processes' [patent_app_type] => B1 [patent_app_number] => 09/375583 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4413 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359293.pdf [firstpage_image] =>[orig_patent_app_number] => 09375583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419396 [patent_doc_number] => 06525397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology' [patent_app_type] => B1 [patent_app_number] => 09/376161 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4066 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525397.pdf [firstpage_image] =>[orig_patent_app_number] => 09376161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1035093 [patent_doc_number] => 06876053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Isolation structure configurations for modifying stresses in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 09/374502 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 4561 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/876/06876053.pdf [firstpage_image] =>[orig_patent_app_number] => 09374502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4388407 [patent_doc_number] => 06278182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Lead frame type semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/372923 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1956 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278182.pdf [firstpage_image] =>[orig_patent_app_number] => 372923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4360922 [patent_doc_number] => 06218725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Bipolar transistors with isolation trenches to reduce collector resistance' [patent_app_type] => 1 [patent_app_number] => 9/371041 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3186 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218725.pdf [firstpage_image] =>[orig_patent_app_number] => 371041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495485 [patent_doc_number] => 06342722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Integrated circuit having air gaps between dielectric and conducting lines' [patent_app_type] => B1 [patent_app_number] => 09/369082 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2080 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342722.pdf [firstpage_image] =>[orig_patent_app_number] => 09369082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424755 [patent_doc_number] => 06225679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method and apparatus for protecting a device against voltage surges' [patent_app_type] => 1 [patent_app_number] => 9/363231 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3107 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225679.pdf [firstpage_image] =>[orig_patent_app_number] => 363231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4385606 [patent_doc_number] => 06303970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Semiconductor device with a plurality of fuses' [patent_app_type] => 1 [patent_app_number] => 9/345691 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1475 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303970.pdf [firstpage_image] =>[orig_patent_app_number] => 345691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1534541 [patent_doc_number] => 06410948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Memory cell arrays comprising intersecting slanted portions' [patent_app_type] => B1 [patent_app_number] => 09/340983 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 6321 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410948.pdf [firstpage_image] =>[orig_patent_app_number] => 09340983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1502312 [patent_doc_number] => 06486527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter' [patent_app_type] => B1 [patent_app_number] => 09/344613 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4529 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486527.pdf [firstpage_image] =>[orig_patent_app_number] => 09344613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317723 [patent_doc_number] => 06316798 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Ferroelectric memory device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/331670 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3452 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316798.pdf [firstpage_image] =>[orig_patent_app_number] => 331670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568355 [patent_doc_number] => 06376868 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Multi-layered gate for a CMOS imager' [patent_app_type] => B1 [patent_app_number] => 09/333011 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7528 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376868.pdf [firstpage_image] =>[orig_patent_app_number] => 09333011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257596 [patent_doc_number] => 06208011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Voltage-controlled power semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/325383 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4520 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208011.pdf [firstpage_image] =>[orig_patent_app_number] => 325383 [rel_patent_id] =>[rel_patent_doc_number] =>)