
John Zazworsky
Examiner (ID: 6934)
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2504, 2107, 2607 |
| Total Applications | 1204 |
| Issued Applications | 1067 |
| Pending Applications | 0 |
| Abandoned Applications | 137 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4366310
[patent_doc_number] => 06255705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Producing devices having both active matrix display circuits and peripheral circuits on a same substrate'
[patent_app_type] => 1
[patent_app_number] => 9/158801
[patent_app_country] => US
[patent_app_date] => 1998-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 22
[patent_no_of_words] => 10759
[patent_no_of_claims] => 74
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/255/06255705.pdf
[firstpage_image] =>[orig_patent_app_number] => 158801
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158801 | Producing devices having both active matrix display circuits and peripheral circuits on a same substrate | Sep 21, 1998 | Issued |
Array
(
[id] => 3953840
[patent_doc_number] => 05977599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Formation of a metal via using a raised metal plug structure'
[patent_app_type] => 1
[patent_app_number] => 9/157511
[patent_app_country] => US
[patent_app_date] => 1998-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 3705
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/977/05977599.pdf
[firstpage_image] =>[orig_patent_app_number] => 157511
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157511 | Formation of a metal via using a raised metal plug structure | Sep 20, 1998 | Issued |
Array
(
[id] => 4009539
[patent_doc_number] => 06005277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'ARC layer enhancement for reducing metal loss during via etch'
[patent_app_type] => 1
[patent_app_number] => 9/157512
[patent_app_country] => US
[patent_app_date] => 1998-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2784
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/005/06005277.pdf
[firstpage_image] =>[orig_patent_app_number] => 157512
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157512 | ARC layer enhancement for reducing metal loss during via etch | Sep 20, 1998 | Issued |
Array
(
[id] => 4300017
[patent_doc_number] => 06180993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Ion repulsion structure for fuse window'
[patent_app_type] => 1
[patent_app_number] => 9/153870
[patent_app_country] => US
[patent_app_date] => 1998-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2881
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/180/06180993.pdf
[firstpage_image] =>[orig_patent_app_number] => 153870
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/153870 | Ion repulsion structure for fuse window | Sep 14, 1998 | Issued |
Array
(
[id] => 4132570
[patent_doc_number] => 06127718
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/146682
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 7754
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/127/06127718.pdf
[firstpage_image] =>[orig_patent_app_number] => 146682
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146682 | Semiconductor device and method of manufacturing the same | Sep 2, 1998 | Issued |
Array
(
[id] => 4091473
[patent_doc_number] => 06018175
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Gapped-plate capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/148032
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 73
[patent_no_of_words] => 9218
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/018/06018175.pdf
[firstpage_image] =>[orig_patent_app_number] => 148032
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/148032 | Gapped-plate capacitor | Sep 2, 1998 | Issued |
Array
(
[id] => 1069204
[patent_doc_number] => 06844600
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-18
[patent_title] => 'ESD/EOS protection structure for integrated circuit devices'
[patent_app_type] => utility
[patent_app_number] => 09/146851
[patent_app_country] => US
[patent_app_date] => 1998-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 40
[patent_no_of_words] => 4987
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/844/06844600.pdf
[firstpage_image] =>[orig_patent_app_number] => 09146851
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/146851 | ESD/EOS protection structure for integrated circuit devices | Sep 2, 1998 | Issued |
Array
(
[id] => 4411743
[patent_doc_number] => 06172400
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'MOS transistor with shield coplanar with gate electrode'
[patent_app_type] => 1
[patent_app_number] => 9/139532
[patent_app_country] => US
[patent_app_date] => 1998-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 1970
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/172/06172400.pdf
[firstpage_image] =>[orig_patent_app_number] => 139532
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/139532 | MOS transistor with shield coplanar with gate electrode | Aug 24, 1998 | Issued |
Array
(
[id] => 4265023
[patent_doc_number] => 06204549
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Overvoltage protection device'
[patent_app_type] => 1
[patent_app_number] => 9/138441
[patent_app_country] => US
[patent_app_date] => 1998-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2643
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/204/06204549.pdf
[firstpage_image] =>[orig_patent_app_number] => 138441
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/138441 | Overvoltage protection device | Aug 20, 1998 | Issued |
Array
(
[id] => 4163486
[patent_doc_number] => 06114758
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Article comprising a superconducting RF filter'
[patent_app_type] => 1
[patent_app_number] => 9/138102
[patent_app_country] => US
[patent_app_date] => 1998-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 4273
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114758.pdf
[firstpage_image] =>[orig_patent_app_number] => 138102
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/138102 | Article comprising a superconducting RF filter | Aug 20, 1998 | Issued |
Array
(
[id] => 4309444
[patent_doc_number] => 06188100
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Concentric container fin capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/136892
[patent_app_country] => US
[patent_app_date] => 1998-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 3424
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/188/06188100.pdf
[firstpage_image] =>[orig_patent_app_number] => 136892
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136892 | Concentric container fin capacitor | Aug 18, 1998 | Issued |
Array
(
[id] => 4324860
[patent_doc_number] => 06249037
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry'
[patent_app_type] => 1
[patent_app_number] => 9/135392
[patent_app_country] => US
[patent_app_date] => 1998-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2047
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/249/06249037.pdf
[firstpage_image] =>[orig_patent_app_number] => 135392
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135392 | Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry | Aug 16, 1998 | Issued |
Array
(
[id] => 4366040
[patent_doc_number] => 06255686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof'
[patent_app_type] => 1
[patent_app_number] => 9/124852
[patent_app_country] => US
[patent_app_date] => 1998-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 71
[patent_no_of_words] => 8964
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/255/06255686.pdf
[firstpage_image] =>[orig_patent_app_number] => 124852
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124852 | Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof | Jul 29, 1998 | Issued |
Array
(
[id] => 4257241
[patent_doc_number] => 06207988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/123982
[patent_app_country] => US
[patent_app_date] => 1998-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 47
[patent_no_of_words] => 7271
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/207/06207988.pdf
[firstpage_image] =>[orig_patent_app_number] => 123982
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/123982 | Semiconductor device and method for fabricating the same | Jul 28, 1998 | Issued |
Array
(
[id] => 4412786
[patent_doc_number] => 06239462
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same'
[patent_app_type] => 1
[patent_app_number] => 9/120893
[patent_app_country] => US
[patent_app_date] => 1998-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 34
[patent_no_of_words] => 9099
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/239/06239462.pdf
[firstpage_image] =>[orig_patent_app_number] => 120893
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120893 | Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same | Jul 22, 1998 | Issued |
Array
(
[id] => 1158411
[patent_doc_number] => 06765257
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-20
[patent_title] => 'Implanted vertical source-line under straight stack for flash eprom'
[patent_app_type] => B1
[patent_app_number] => 09/120712
[patent_app_country] => US
[patent_app_date] => 1998-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2662
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/765/06765257.pdf
[firstpage_image] =>[orig_patent_app_number] => 09120712
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/120712 | Implanted vertical source-line under straight stack for flash eprom | Jul 21, 1998 | Issued |
Array
(
[id] => 4179451
[patent_doc_number] => 06084252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Semiconductor light emitting device'
[patent_app_type] => 1
[patent_app_number] => 9/113302
[patent_app_country] => US
[patent_app_date] => 1998-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4742
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/084/06084252.pdf
[firstpage_image] =>[orig_patent_app_number] => 113302
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/113302 | Semiconductor light emitting device | Jul 9, 1998 | Issued |
Array
(
[id] => 4161579
[patent_doc_number] => 06104070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Semiconductor device with reduced number of through holes and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/110401
[patent_app_country] => US
[patent_app_date] => 1998-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4014
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/104/06104070.pdf
[firstpage_image] =>[orig_patent_app_number] => 110401
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110401 | Semiconductor device with reduced number of through holes and method of manufacturing the same | Jul 5, 1998 | Issued |
Array
(
[id] => 4103442
[patent_doc_number] => 06049137
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Readable alignment mark structure formed using enhanced chemical mechanical polishing'
[patent_app_type] => 1
[patent_app_number] => 9/106331
[patent_app_country] => US
[patent_app_date] => 1998-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 4279
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049137.pdf
[firstpage_image] =>[orig_patent_app_number] => 106331
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/106331 | Readable alignment mark structure formed using enhanced chemical mechanical polishing | Jun 28, 1998 | Issued |
Array
(
[id] => 4244183
[patent_doc_number] => 06081031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Semiconductor package consisting of multiple conductive layers'
[patent_app_type] => 1
[patent_app_number] => 9/106472
[patent_app_country] => US
[patent_app_date] => 1998-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3738
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/081/06081031.pdf
[firstpage_image] =>[orig_patent_app_number] => 106472
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/106472 | Semiconductor package consisting of multiple conductive layers | Jun 28, 1998 | Issued |