Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14125899 [patent_doc_number] => 10249815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Electronic device and method for fabricating the same including variable resistance element and lower contact plug with sidewalls aligned to each other [patent_app_type] => utility [patent_app_number] => 15/469266 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469266 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/469266
Electronic device and method for fabricating the same including variable resistance element and lower contact plug with sidewalls aligned to each other Mar 23, 2017 Issued
Array ( [id] => 14177403 [patent_doc_number] => 10262722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Fail-safe input/output (IO) circuit [patent_app_type] => utility [patent_app_number] => 15/447230 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5838 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447230
Fail-safe input/output (IO) circuit Mar 1, 2017 Issued
Array ( [id] => 13056649 [patent_doc_number] => 10049720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Dynamic random access memory (DRAM) [patent_app_type] => utility [patent_app_number] => 15/445331 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 61 [patent_no_of_words] => 21643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445331
Dynamic random access memory (DRAM) Feb 27, 2017 Issued
Array ( [id] => 12229638 [patent_doc_number] => 09916883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Magnetic random access memory using current sense amplifier for reading cell data and related method' [patent_app_type] => utility [patent_app_number] => 15/442139 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442139
Magnetic random access memory using current sense amplifier for reading cell data and related method Feb 23, 2017 Issued
Array ( [id] => 12162221 [patent_doc_number] => 20180033487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'NON-VOLATILE MEMORY WITH FLOATING GATE HAVING PROTRUDING PORTION' [patent_app_type] => utility [patent_app_number] => 15/436829 [patent_app_country] => US [patent_app_date] => 2017-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5948 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436829 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436829
Non-volatile memory with floating gate having protruding portion Feb 18, 2017 Issued
Array ( [id] => 13098629 [patent_doc_number] => 10068657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels [patent_app_type] => utility [patent_app_number] => 15/430299 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 39 [patent_no_of_words] => 17805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430299
Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels Feb 9, 2017 Issued
Array ( [id] => 13349165 [patent_doc_number] => 20180226122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => Contention-Free Dynamic Logic [patent_app_type] => utility [patent_app_number] => 15/424367 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424367 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/424367
Contention-free dynamic logic Feb 2, 2017 Issued
Array ( [id] => 12122116 [patent_doc_number] => 20180005702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'BOOSTER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/412221 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412221
Booster circuit Jan 22, 2017 Issued
Array ( [id] => 11622911 [patent_doc_number] => 20170133098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'FAST SOFT DATA BY DETECTING LEAKAGE CURRENT AND SENSING TIME' [patent_app_type] => utility [patent_app_number] => 15/411040 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/411040
Fast soft data by detecting leakage current and sensing time Jan 19, 2017 Issued
Array ( [id] => 12477171 [patent_doc_number] => 09990976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-05 [patent_title] => Method and apparatus for storing data in a reference layer in magnetoresistive memory cells [patent_app_type] => utility [patent_app_number] => 15/409757 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409757 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409757
Method and apparatus for storing data in a reference layer in magnetoresistive memory cells Jan 18, 2017 Issued
Array ( [id] => 11607781 [patent_doc_number] => 20170125084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING CAL LATENCY FUNCTION' [patent_app_type] => utility [patent_app_number] => 15/403513 [patent_app_country] => US [patent_app_date] => 2017-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7604 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15403513 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/403513
Semiconductor device having CAL latency function Jan 10, 2017 Issued
Array ( [id] => 13018753 [patent_doc_number] => 10032491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Apparatuses and methods for storing a data value in multiple columns [patent_app_type] => utility [patent_app_number] => 15/399315 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 23270 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/399315
Apparatuses and methods for storing a data value in multiple columns Jan 4, 2017 Issued
Array ( [id] => 12174647 [patent_doc_number] => 09892794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Method and apparatus with program suspend using test mode' [patent_app_type] => utility [patent_app_number] => 15/396721 [patent_app_country] => US [patent_app_date] => 2017-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 12166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396721 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396721
Method and apparatus with program suspend using test mode Jan 1, 2017 Issued
Array ( [id] => 12691855 [patent_doc_number] => 20180122451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => FERROELECTRIC RANDOM ACCESS MEMORY (FERAM) ARRAY WITH SEGMENTED PLATE LINES THAT ARE ELECTRICALLY-ISOLATED FROM EACH OTHER [patent_app_type] => utility [patent_app_number] => 15/391991 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391991
Ferroelectric random access memory (FeRAM) array with segmented plate lines that are electrically-isolated from each other Dec 27, 2016 Issued
Array ( [id] => 13145397 [patent_doc_number] => 10090036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Non-volatile memory cell having pinch-off ferroelectric field effect transistor [patent_app_type] => utility [patent_app_number] => 15/385593 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7906 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385593
Non-volatile memory cell having pinch-off ferroelectric field effect transistor Dec 19, 2016 Issued
Array ( [id] => 14491591 [patent_doc_number] => 10332593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Semiconductor memory device configured to sense memory cell threshold voltages in ascending order [patent_app_type] => utility [patent_app_number] => 15/530248 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 39 [patent_no_of_words] => 22126 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15530248 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/530248
Semiconductor memory device configured to sense memory cell threshold voltages in ascending order Dec 15, 2016 Issued
Array ( [id] => 12354594 [patent_doc_number] => 09953708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Memory performing write operation in which a string transistor channel voltage is boosted before applying a program voltage to a word line [patent_app_type] => utility [patent_app_number] => 15/367361 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 9677 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367361 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367361
Memory performing write operation in which a string transistor channel voltage is boosted before applying a program voltage to a word line Dec 1, 2016 Issued
Array ( [id] => 12108852 [patent_doc_number] => 09865340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Enhanced temperature compensation for resistive memory cell circuits' [patent_app_type] => utility [patent_app_number] => 15/366386 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366386 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/366386
Enhanced temperature compensation for resistive memory cell circuits Nov 30, 2016 Issued
Array ( [id] => 11571869 [patent_doc_number] => 20170110512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'Finfet Structures for Programmable Resistive Devices' [patent_app_type] => utility [patent_app_number] => 15/365584 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 26409 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365584
Programmable resistive devices using Finfet structures for selectors Nov 29, 2016 Issued
Array ( [id] => 11502619 [patent_doc_number] => 20170076804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/361778 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8700 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361778 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361778
Memory system including a memory chip configured to receive an erase suspend command and a program suspend command from a controller chip Nov 27, 2016 Issued
Menu