Jon D. Epperson

Array ( [id] => 11817718 [patent_doc_number] => 09721675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-01 [patent_title] => 'Memory device having input circuit and operating method of same' [patent_app_type] => utility [patent_app_number] => 15/346807 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5611 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11502604 [patent_doc_number] => 20170076789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'MEMORY WITH OUTPUT CONTROL' [patent_app_type] => utility [patent_app_number] => 15/345552 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15629 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15345552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11622890 [patent_doc_number] => 20170133077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'ELECTROENTROPIC MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/343779 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11753218 [patent_doc_number] => 09711236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Methods and apparatus to program multi-level cell memory using target-only verify' [patent_app_type] => utility [patent_app_number] => 15/299008 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 19110 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15299008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13145375 [patent_doc_number] => 10090025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Discharging electric charge in integrated circuit unless in-specification condition(s) detected [patent_app_type] => utility [patent_app_number] => 15/292616 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12395625 [patent_doc_number] => 09966127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Compensating for variations in selector threshold voltages [patent_app_type] => utility [patent_app_number] => 15/291711 [patent_app_country] => US [patent_app_date] => 2016-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 17866 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15291711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11687189 [patent_doc_number] => 09685239 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-20 [patent_title] => 'Field sub-bitline nor flash array' [patent_app_type] => utility [patent_app_number] => 15/291932 [patent_app_country] => US [patent_app_date] => 2016-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4108 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15291932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11918180 [patent_doc_number] => 09786371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Power-on reset circuit with variable detection reference and semiconductor memory device including the same' [patent_app_type] => utility [patent_app_number] => 15/290702 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11681103 [patent_doc_number] => 09679637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-13 [patent_title] => 'Single-ended memory device with differential sensing' [patent_app_type] => utility [patent_app_number] => 15/288235 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11599495 [patent_doc_number] => 09646671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-09 [patent_title] => 'Systems and methods for managing write voltages in a cross-point memory array' [patent_app_type] => utility [patent_app_number] => 15/288886 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11817694 [patent_doc_number] => 09721651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Write driver and level shifter having shared transistors' [patent_app_type] => utility [patent_app_number] => 15/281312 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11592648 [patent_doc_number] => 20170117060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'MULTI-PORT MEMORY, SEMICONDUCTOR DEVICE, AND MEMORY MACRO-CELL' [patent_app_type] => utility [patent_app_number] => 15/281947 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10710 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281947 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11753183 [patent_doc_number] => 09711201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Reconfigurable and writable magnetic charge crystals' [patent_app_type] => utility [patent_app_number] => 15/280915 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 67 [patent_no_of_words] => 6422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12012460 [patent_doc_number] => 09805780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Nonvolatile memory with magnetoresistive element and transistor' [patent_app_type] => utility [patent_app_number] => 15/267715 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 12431 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11854670 [patent_doc_number] => 20170229162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'NONVOLATILE RAM' [patent_app_type] => utility [patent_app_number] => 15/266393 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11701566 [patent_doc_number] => 09691489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-27 [patent_title] => 'Nonvolatile semiconductor memory device with first and second read operations with different read voltages' [patent_app_type] => utility [patent_app_number] => 15/263518 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 10878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15263518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14204569 [patent_doc_number] => 10269402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Magnetic topological soliton detection [patent_app_type] => utility [patent_app_number] => 15/260718 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 8112 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15260718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14366455 [patent_doc_number] => 10304539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Method of performing a write operation based on an idle time [patent_app_type] => utility [patent_app_number] => 15/259743 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 13958 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11564442 [patent_doc_number] => 09627035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Fail-safe I/O to achieve ultra low system power' [patent_app_type] => utility [patent_app_number] => 15/236797 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11687175 [patent_doc_number] => 09685225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Semiconductor storage device for controlling word lines independently of power-on sequence' [patent_app_type] => utility [patent_app_number] => 15/232216 [patent_app_country] => US [patent_app_date] => 2016-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3857 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232216 [rel_patent_id] =>[rel_patent_doc_number] =>)