Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11452991 [patent_doc_number] => 09576639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Method for controlling a semiconductor device having CAL latency function' [patent_app_type] => utility [patent_app_number] => 15/229417 [patent_app_country] => US [patent_app_date] => 2016-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7568 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229417 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/229417
Method for controlling a semiconductor device having CAL latency function Aug 4, 2016 Issued
Array ( [id] => 13056639 [patent_doc_number] => 10049715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Semiconductor storage device and method for writing of the same [patent_app_type] => utility [patent_app_number] => 15/568811 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7322 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15568811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/568811
Semiconductor storage device and method for writing of the same Jul 31, 2016 Issued
Array ( [id] => 14737903 [patent_doc_number] => 10388360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Utilization of data stored in an edge section of an array [patent_app_type] => utility [patent_app_number] => 15/213755 [patent_app_country] => US [patent_app_date] => 2016-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17240 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15213755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/213755
Utilization of data stored in an edge section of an array Jul 18, 2016 Issued
Array ( [id] => 11551331 [patent_doc_number] => 09620185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-11 [patent_title] => 'Voltage supply devices generating voltages applied to nonvolatile memory cells' [patent_app_type] => utility [patent_app_number] => 15/212017 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15149 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212017
Voltage supply devices generating voltages applied to nonvolatile memory cells Jul 14, 2016 Issued
Array ( [id] => 11564474 [patent_doc_number] => 09627066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Non volatile memory cell and memory array' [patent_app_type] => utility [patent_app_number] => 15/210709 [patent_app_country] => US [patent_app_date] => 2016-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8679 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15210709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/210709
Non volatile memory cell and memory array Jul 13, 2016 Issued
Array ( [id] => 11539298 [patent_doc_number] => 09613714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-04 [patent_title] => 'One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method' [patent_app_type] => utility [patent_app_number] => 15/209079 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 77 [patent_no_of_words] => 29357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209079 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209079
One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method Jul 12, 2016 Issued
Array ( [id] => 12019496 [patent_doc_number] => 09812205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'MTJ-based content addressable memory with measured resistance across matchlines' [patent_app_type] => utility [patent_app_number] => 15/205813 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15205813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/205813
MTJ-based content addressable memory with measured resistance across matchlines Jul 7, 2016 Issued
Array ( [id] => 11125111 [patent_doc_number] => 20160322085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/206106 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15206106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/206106
Semiconductor memory device having inverting circuit and controlling method there of Jul 7, 2016 Issued
Array ( [id] => 11753192 [patent_doc_number] => 09711210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Low power high performance electrical circuits' [patent_app_type] => utility [patent_app_number] => 15/201465 [patent_app_country] => US [patent_app_date] => 2016-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 41 [patent_no_of_words] => 11294 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201465 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201465
Low power high performance electrical circuits Jul 2, 2016 Issued
Array ( [id] => 13651499 [patent_doc_number] => 09852065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-26 [patent_title] => Method and apparatus for reducing data program completion overhead in NAND flash [patent_app_type] => utility [patent_app_number] => 15/195328 [patent_app_country] => US [patent_app_date] => 2016-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/195328
Method and apparatus for reducing data program completion overhead in NAND flash Jun 27, 2016 Issued
Array ( [id] => 11087442 [patent_doc_number] => 20160284409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING A MEMORY STRING THAT INCLUDES A TRANSISTOR HAVING A CHARGE STORED THEREIN TO INDICATE THE MEMORY STRING IS DEFECTIVE' [patent_app_type] => utility [patent_app_number] => 15/181096 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 21452 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15181096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/181096
Semiconductor memory device having a memory string that includes a transistor having a charge stored therein to indicate the memory string is defective Jun 12, 2016 Issued
Array ( [id] => 11502616 [patent_doc_number] => 20170076801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/174527 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174527
Memory system Jun 5, 2016 Issued
Array ( [id] => 11087445 [patent_doc_number] => 20160284412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'MEMORY SYSTEM AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/174183 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174183
Memory system and driving method thereof using at least two zone voltages Jun 5, 2016 Issued
Array ( [id] => 12095300 [patent_doc_number] => 20170352393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'EMULATED MULTIPORT MEMORY ELEMENT CIRCUITRY WITH EXCLUSIVE-OR BASED CONTROL CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 15/174460 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174460
Emulated multiport memory element circuitry with exclusive-OR based control circuitry Jun 5, 2016 Issued
Array ( [id] => 11876212 [patent_doc_number] => 09747992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-29 [patent_title] => 'Non-volatile memory with customized control of injection type of disturb during read operations' [patent_app_type] => utility [patent_app_number] => 15/172671 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 15763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172671 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/172671
Non-volatile memory with customized control of injection type of disturb during read operations Jun 2, 2016 Issued
Array ( [id] => 11753220 [patent_doc_number] => 09711239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Data independent periodic calibration using per-pin VREF correction technique for single-ended signaling' [patent_app_type] => utility [patent_app_number] => 15/169156 [patent_app_country] => US [patent_app_date] => 2016-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15169156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/169156
Data independent periodic calibration using per-pin VREF correction technique for single-ended signaling May 30, 2016 Issued
Array ( [id] => 11599506 [patent_doc_number] => 09646682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-09 [patent_title] => 'Reciprocal quantum logic (RQL) sense amplifier' [patent_app_type] => utility [patent_app_number] => 15/167317 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15167317 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/167317
Reciprocal quantum logic (RQL) sense amplifier May 26, 2016 Issued
Array ( [id] => 12989278 [patent_doc_number] => 20170345485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/162711 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162711 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/162711
Memory read stability enhancement with short segmented bit line architecture May 23, 2016 Issued
Array ( [id] => 11070994 [patent_doc_number] => 20160267958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'MISMATCH AND NOISE INSENSITIVE STT MRAM' [patent_app_type] => utility [patent_app_number] => 15/163268 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163268
Mismatch and noise insensitive sense amplifier circuit for STT MRAM May 23, 2016 Issued
Array ( [id] => 11273513 [patent_doc_number] => 20160336059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/153175 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 24609 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15153175 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/153175
Electronic device May 11, 2016 Issued
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