Jon D. Epperson

Array ( [id] => 11775859 [patent_doc_number] => 09384804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-05 [patent_title] => 'Semiconductor device and semiconductor system' [patent_app_type] => utility [patent_app_number] => 14/718190 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5682 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10825875 [patent_doc_number] => 20160172043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/702413 [patent_app_country] => US [patent_app_date] => 2015-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10418200 [patent_doc_number] => 20150303210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'Lithography-friendly Local Read Circuit for NAND Flash Memory Devices and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/699831 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10218 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597081 [patent_doc_number] => 09318175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-19 [patent_title] => 'Word line driver circuit for semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/699783 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8996 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11775851 [patent_doc_number] => 09384795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-05 [patent_title] => 'Fully valid-gated read and write for low power array' [patent_app_type] => utility [patent_app_number] => 14/698843 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8561 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14698843 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11764948 [patent_doc_number] => 09373388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'Sense amplifier with pulsed control for pull-up transistors' [patent_app_type] => utility [patent_app_number] => 14/699957 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3825 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10556880 [patent_doc_number] => 09281082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-08 [patent_title] => 'Semiconductor memory device including redundancy circuit and fuse circuit' [patent_app_type] => utility [patent_app_number] => 14/699707 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6018 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11125124 [patent_doc_number] => 20160322098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MEMORY DEVICE WITH STABLE WRITING AND/OR READING OPERATION' [patent_app_type] => utility [patent_app_number] => 14/700135 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11246231 [patent_doc_number] => 09472275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Method of operating memory device using different read conditions' [patent_app_type] => utility [patent_app_number] => 14/698175 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 16359 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14698175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10576762 [patent_doc_number] => 09299413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Semiconductor systems' [patent_app_type] => utility [patent_app_number] => 14/698263 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5136 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14698263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10794878 [patent_doc_number] => 20160141035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/692323 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5694 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10983960 [patent_doc_number] => 20160180904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/691303 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10327879 [patent_doc_number] => 20150212883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'ON CHIP DYNAMIC READ LEVEL SCAN AND ERROR DETECTION FOR NONVOLATILE STORAGE' [patent_app_type] => utility [patent_app_number] => 14/681800 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 17152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10794869 [patent_doc_number] => 20160141026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'MEMORY SYSTEM AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/678555 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14678555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10328899 [patent_doc_number] => 20150213903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/677111 [patent_app_country] => US [patent_app_date] => 2015-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10854 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14677111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10518588 [patent_doc_number] => 09245642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-26 [patent_title] => 'Temperature dependent voltage to unselected drain side select transistor during program of 3D NAND' [patent_app_type] => utility [patent_app_number] => 14/673265 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 17517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12293442 [patent_doc_number] => 09934833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Memory circuit having tracking circuit including series-connected transistors [patent_app_type] => utility [patent_app_number] => 14/666371 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11187337 [patent_doc_number] => 09418745 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Rebalancing in twin cell memory schemes to enable multiple writes' [patent_app_type] => utility [patent_app_number] => 14/661383 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 11241 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14661383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14702859 [patent_doc_number] => 10379169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Battery capacity estimating apparatus and battery capacity estimating method thereof [patent_app_type] => utility [patent_app_number] => 14/642771 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3244 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10433013 [patent_doc_number] => 20150318025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'MEMORY DEVICE WITH REDUCED OPERATING CURRENT' [patent_app_type] => utility [patent_app_number] => 14/637647 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637647 [rel_patent_id] =>[rel_patent_doc_number] =>)