Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10624183 [patent_doc_number] => 09343131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Mismatch and noise insensitive sense amplifier circuit for STT MRAM' [patent_app_type] => utility [patent_app_number] => 14/629875 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8807 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629875
Mismatch and noise insensitive sense amplifier circuit for STT MRAM Feb 23, 2015 Issued
Array ( [id] => 14456361 [patent_doc_number] => 10324137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Intelligent method for calibrating battery capacity [patent_app_type] => utility [patent_app_number] => 14/630348 [patent_app_country] => US [patent_app_date] => 2015-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14630348 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/630348
Intelligent method for calibrating battery capacity Feb 23, 2015 Issued
Array ( [id] => 10277063 [patent_doc_number] => 20150162060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'MEMORY MACRO WITH A VOLTAGE KEEPER' [patent_app_type] => utility [patent_app_number] => 14/620769 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620769
Memory macro with a voltage keeper Feb 11, 2015 Issued
Array ( [id] => 10508264 [patent_doc_number] => 09236139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-12 [patent_title] => 'Reduced current program verify in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/619875 [patent_app_country] => US [patent_app_date] => 2015-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 39 [patent_no_of_words] => 22465 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14619875 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/619875
Reduced current program verify in non-volatile memory Feb 10, 2015 Issued
Array ( [id] => 10261486 [patent_doc_number] => 20150146483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'DIFFERENTIAL CURRENT SENSING SCHEME FOR MAGNETIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 14/611572 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611572 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/611572
Differential current sensing scheme for magnetic random access memory Feb 1, 2015 Issued
Array ( [id] => 10253887 [patent_doc_number] => 20150138883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-21 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/607612 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9349 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607612 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607612
Non-volatile semiconductor device Jan 27, 2015 Issued
Array ( [id] => 10195589 [patent_doc_number] => 09224502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-29 [patent_title] => 'Techniques for detection and treating memory hole to local interconnect marginality defects' [patent_app_type] => utility [patent_app_number] => 14/596751 [patent_app_country] => US [patent_app_date] => 2015-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 41 [patent_no_of_words] => 15668 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14596751 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/596751
Techniques for detection and treating memory hole to local interconnect marginality defects Jan 13, 2015 Issued
Array ( [id] => 10239534 [patent_doc_number] => 20150124528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/596639 [patent_app_country] => US [patent_app_date] => 2015-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 21302 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14596639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/596639
Semiconductor memory device having a memory string that includes a transistor having a charge stored therein to indicate the memory string is defective Jan 13, 2015 Issued
Array ( [id] => 11239697 [patent_doc_number] => 09466342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof' [patent_app_type] => utility [patent_app_number] => 14/593395 [patent_app_country] => US [patent_app_date] => 2015-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593395 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/593395
Transistors with source and word line voltage adjusting circuitry for controlling leakage currents and its method thereof Jan 8, 2015 Issued
Array ( [id] => 10666749 [patent_doc_number] => 20160012894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'NON-VOLATILE MEMORY AND COLUMN DECODER THEREOF' [patent_app_type] => utility [patent_app_number] => 14/592477 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8229 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592477 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/592477
Non-volatile memory and associated memory array, row decoder, column decoder, write buffer and sensing circuit Jan 7, 2015 Issued
Array ( [id] => 10232086 [patent_doc_number] => 20150117080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'MULTI-CHIP PACKAGE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/590626 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6084 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590626
Multi-chip package and memory system Jan 5, 2015 Issued
Array ( [id] => 10502243 [patent_doc_number] => 09230645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Apparatus and methods for forming a memory cell using charge monitoring' [patent_app_type] => utility [patent_app_number] => 14/588593 [patent_app_country] => US [patent_app_date] => 2015-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14588593 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/588593
Apparatus and methods for forming a memory cell using charge monitoring Jan 1, 2015 Issued
Array ( [id] => 10597091 [patent_doc_number] => 09318186 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-19 [patent_title] => 'DRAM wordline control circuit, DRAM module and method of controlling DRAM wordline voltage' [patent_app_type] => utility [patent_app_number] => 14/586995 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2480 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14586995 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/586995
DRAM wordline control circuit, DRAM module and method of controlling DRAM wordline voltage Dec 30, 2014 Issued
Array ( [id] => 11125110 [patent_doc_number] => 20160322084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'EXTENSIBLE CONFIGURABLE FPGA STORAGE STRUCTURE AND FPGA DEVICE' [patent_app_type] => utility [patent_app_number] => 14/758357 [patent_app_country] => US [patent_app_date] => 2014-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4924 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14758357 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/758357
Extensible configurable FPGA storage structure and FPGA device Dec 29, 2014 Issued
Array ( [id] => 10556841 [patent_doc_number] => 09281043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-08 [patent_title] => 'Resistive memory write circuitry with bit line drive strength based on storage cell line resistance' [patent_app_type] => utility [patent_app_number] => 14/582745 [patent_app_country] => US [patent_app_date] => 2014-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4225 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582745
Resistive memory write circuitry with bit line drive strength based on storage cell line resistance Dec 23, 2014 Issued
Array ( [id] => 10171870 [patent_doc_number] => 09202582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-01 [patent_title] => 'Flash-memory low-speed read mode control circuit' [patent_app_type] => utility [patent_app_number] => 14/578555 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3734 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 742 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578555 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578555
Flash-memory low-speed read mode control circuit Dec 21, 2014 Issued
Array ( [id] => 10525371 [patent_doc_number] => 09251890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-02 [patent_title] => 'Bias temperature instability state detection and correction' [patent_app_type] => utility [patent_app_number] => 14/577113 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577113 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577113
Bias temperature instability state detection and correction Dec 18, 2014 Issued
Array ( [id] => 10165150 [patent_doc_number] => 09196377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-24 [patent_title] => 'Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays' [patent_app_type] => utility [patent_app_number] => 14/572127 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13827 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572127
Anti-fuse type one-time programmable memory cell and anti-fuse type one-time programmable memory cell arrays Dec 15, 2014 Issued
Array ( [id] => 11187353 [patent_doc_number] => 09418761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Apparatus for boosting source-line voltage to reduce leakage in resistive memories' [patent_app_type] => utility [patent_app_number] => 14/569573 [patent_app_country] => US [patent_app_date] => 2014-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8098 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569573 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/569573
Apparatus for boosting source-line voltage to reduce leakage in resistive memories Dec 11, 2014 Issued
Array ( [id] => 10207485 [patent_doc_number] => 20150092473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/563605 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6059 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14563605 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/563605
Semiconductor memory device Dec 7, 2014 Issued
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