Jon D. Epperson

Array ( [id] => 6646480 [patent_doc_number] => 20100174854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION' [patent_app_type] => utility [patent_app_number] => 12/635280 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9296 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174854.pdf [firstpage_image] =>[orig_patent_app_number] => 12635280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8376726 [patent_doc_number] => 08259526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Semiconductor device performing serial parallel conversion' [patent_app_type] => utility [patent_app_number] => 12/627768 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8298 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12627768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4438760 [patent_doc_number] => 07898862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Memory card, semiconductor device, and method of controlling memory card' [patent_app_type] => utility [patent_app_number] => 12/626787 [patent_app_country] => US [patent_app_date] => 2009-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 9986 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898862.pdf [firstpage_image] =>[orig_patent_app_number] => 12626787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6298540 [patent_doc_number] => 20100067309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'EFFICIENT ERASE ALGORITHM FOR SONOS-TYPE NAND FLASH' [patent_app_type] => utility [patent_app_number] => 12/625438 [patent_app_country] => US [patent_app_date] => 2009-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5907 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20100067309.pdf [firstpage_image] =>[orig_patent_app_number] => 12625438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6218946 [patent_doc_number] => 20100054041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO A RATE OF PROGRAMMING OR ERASING' [patent_app_type] => utility [patent_app_number] => 12/614626 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8972 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054041.pdf [firstpage_image] =>[orig_patent_app_number] => 12614626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6565130 [patent_doc_number] => 20100046299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/612139 [patent_app_country] => US [patent_app_date] => 2009-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046299.pdf [firstpage_image] =>[orig_patent_app_number] => 12612139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6201116 [patent_doc_number] => 20110063902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => '2T2R-1T1R MIX MODE PHASE CHANGE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/561556 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063902.pdf [firstpage_image] =>[orig_patent_app_number] => 12561556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8154803 [patent_doc_number] => 08169830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Sensing for all bit line architecture in a memory device' [patent_app_type] => utility [patent_app_number] => 12/561692 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3096 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169830.pdf [firstpage_image] =>[orig_patent_app_number] => 12561692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4559874 [patent_doc_number] => 07961521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Sensing circuit for flash memory device operating at low power supply voltage' [patent_app_type] => utility [patent_app_number] => 12/560728 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4140 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961521.pdf [firstpage_image] =>[orig_patent_app_number] => 12560728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4452846 [patent_doc_number] => 07965536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Ferroelectric memory device' [patent_app_type] => utility [patent_app_number] => 12/560206 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9792 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965536.pdf [firstpage_image] =>[orig_patent_app_number] => 12560206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6201119 [patent_doc_number] => 20110063905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'MULTI-VALUED ROM USING CARBON-NANOTUBE AND NANOWIRE FET' [patent_app_type] => utility [patent_app_number] => 12/560040 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063905.pdf [firstpage_image] =>[orig_patent_app_number] => 12560040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6298558 [patent_doc_number] => 20100067313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/560224 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20100067313.pdf [firstpage_image] =>[orig_patent_app_number] => 12560224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4601716 [patent_doc_number] => 07978555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/560170 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8569 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978555.pdf [firstpage_image] =>[orig_patent_app_number] => 12560170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6201107 [patent_doc_number] => 20110063893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING' [patent_app_type] => utility [patent_app_number] => 12/558816 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063893.pdf [firstpage_image] =>[orig_patent_app_number] => 12558816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4465102 [patent_doc_number] => 07881149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Write latency tracking using a delay lock loop in a synchronous DRAM' [patent_app_type] => utility [patent_app_number] => 12/551876 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3191 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/881/07881149.pdf [firstpage_image] =>[orig_patent_app_number] => 12551876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6023161 [patent_doc_number] => 20110051487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Read only memory cell for storing a multiple bit value' [patent_app_type] => utility [patent_app_number] => 12/461966 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4537 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051487.pdf [firstpage_image] =>[orig_patent_app_number] => 12461966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6194554 [patent_doc_number] => 20110026308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'CELL STRUCTURE FOR DUAL PORT SRAM' [patent_app_type] => utility [patent_app_number] => 12/533394 [patent_app_country] => US [patent_app_date] => 2009-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4569 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20110026308.pdf [firstpage_image] =>[orig_patent_app_number] => 12533394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4625578 [patent_doc_number] => 08004884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Iterative write pausing techniques to improve read latency of memory systems' [patent_app_type] => utility [patent_app_number] => 12/533548 [patent_app_country] => US [patent_app_date] => 2009-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7882 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004884.pdf [firstpage_image] =>[orig_patent_app_number] => 12533548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7556457 [patent_doc_number] => 08068361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Systems and methods for performing a program-verify process on a nonvolatile memory by selectively pre-charging bit lines associated with memory cells during the verify operations' [patent_app_type] => utility [patent_app_number] => 12/533720 [patent_app_country] => US [patent_app_date] => 2009-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 11502 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/068/08068361.pdf [firstpage_image] =>[orig_patent_app_number] => 12533720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5991793 [patent_doc_number] => 20110013446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'REFRESH CIRCUITRY FOR PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/503566 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20110013446.pdf [firstpage_image] =>[orig_patent_app_number] => 12503566 [rel_patent_id] =>[rel_patent_doc_number] =>)