Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 237035 [patent_doc_number] => 07596018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Spin memory with write pulse' [patent_app_type] => utility [patent_app_number] => 11/929495 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 11258 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596018.pdf [firstpage_image] =>[orig_patent_app_number] => 11929495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/929495
Spin memory with write pulse Oct 29, 2007 Issued
Array ( [id] => 5329297 [patent_doc_number] => 20090109774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'TEST METHOD AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/928790 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6637 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109774.pdf [firstpage_image] =>[orig_patent_app_number] => 11928790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/928790
Test method and semiconductor device Oct 29, 2007 Issued
Array ( [id] => 5329250 [patent_doc_number] => 20090109727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Erase, programming and leakage characteristics of a resistive memory device' [patent_app_type] => utility [patent_app_number] => 11/980116 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3251 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20090109727.pdf [firstpage_image] =>[orig_patent_app_number] => 11980116 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980116
Erase, programming and leakage characteristics of a resistive memory device Oct 29, 2007 Issued
Array ( [id] => 4732510 [patent_doc_number] => 20080049489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Multi-Bit Spin Memory' [patent_app_type] => utility [patent_app_number] => 11/929577 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049489.pdf [firstpage_image] =>[orig_patent_app_number] => 11929577 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/929577
Multi-bit spin memory Oct 29, 2007 Issued
Array ( [id] => 4732503 [patent_doc_number] => 20080049482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'COMPARE CIRCUIT FOR A CONTENT ADDRESSABLE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 11/925208 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9628 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049482.pdf [firstpage_image] =>[orig_patent_app_number] => 11925208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/925208
Compare circuit for a content addressable memory cell Oct 25, 2007 Issued
Array ( [id] => 5584188 [patent_doc_number] => 20090103390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Three Dimensional Twisted Bitline Architecture for Multi-port Memory' [patent_app_type] => utility [patent_app_number] => 11/875173 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103390.pdf [firstpage_image] =>[orig_patent_app_number] => 11875173 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/875173
Three dimensional twisted bitline architecture for multi-port memory Oct 18, 2007 Issued
Array ( [id] => 4744535 [patent_doc_number] => 20080089137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/873254 [patent_app_country] => US [patent_app_date] => 2007-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 32180 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20080089137.pdf [firstpage_image] =>[orig_patent_app_number] => 11873254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873254
Semiconductor device Oct 15, 2007 Issued
Array ( [id] => 4743326 [patent_doc_number] => 20080087927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Semiconductor memory device with dual storage node and fabricating and operating methods thereof' [patent_app_type] => utility [patent_app_number] => 11/907183 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6085 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20080087927.pdf [firstpage_image] =>[orig_patent_app_number] => 11907183 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907183
Semiconductor memory device with dual storage node and fabricating and operating methods thereof Oct 9, 2007 Issued
Array ( [id] => 4898096 [patent_doc_number] => 20080117709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays' [patent_app_type] => utility [patent_app_number] => 11/863349 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6705 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20080117709.pdf [firstpage_image] =>[orig_patent_app_number] => 11863349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863349
Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays Sep 27, 2007 Abandoned
Array ( [id] => 4770327 [patent_doc_number] => 20080055985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/849752 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 28187 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20080055985.pdf [firstpage_image] =>[orig_patent_app_number] => 11849752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849752
Non-volatile semiconductor memory device Sep 3, 2007 Issued
Array ( [id] => 5321695 [patent_doc_number] => 20090059685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'SRAM BIAS FOR READ AND WRITE' [patent_app_type] => utility [patent_app_number] => 11/848442 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6256 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059685.pdf [firstpage_image] =>[orig_patent_app_number] => 11848442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848442
SRAM bias for read and write Aug 30, 2007 Issued
Array ( [id] => 4770303 [patent_doc_number] => 20080055961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'FERROELECTRIC MEMORY DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/848494 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11770 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20080055961.pdf [firstpage_image] =>[orig_patent_app_number] => 11848494 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848494
Ferroelectric memory device and electronic apparatus Aug 30, 2007 Issued
Array ( [id] => 4770320 [patent_doc_number] => 20080055978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY WITH DUMMY CELL WHICH IS ABSENCE OF A SOURCE/DRAIN REGION' [patent_app_type] => utility [patent_app_number] => 11/847498 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20080055978.pdf [firstpage_image] =>[orig_patent_app_number] => 11847498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847498
Nonvolatile semiconductor memory with dummy cell which is absence of a source/drain region Aug 29, 2007 Issued
Array ( [id] => 5321680 [patent_doc_number] => 20090059670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/847854 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059670.pdf [firstpage_image] =>[orig_patent_app_number] => 11847854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847854
Nonvolatile semiconductor memory device Aug 29, 2007 Issued
Array ( [id] => 4691969 [patent_doc_number] => 20080084739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Method for Programming a Multi-Level Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 11/847980 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8116 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20080084739.pdf [firstpage_image] =>[orig_patent_app_number] => 11847980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847980
Method for programming a multi-level non-volatile memory device Aug 29, 2007 Issued
Array ( [id] => 237039 [patent_doc_number] => 07596022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Method for programming a multi-level non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 11/848014 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7138 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596022.pdf [firstpage_image] =>[orig_patent_app_number] => 11848014 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848014
Method for programming a multi-level non-volatile memory device Aug 29, 2007 Issued
Array ( [id] => 4920587 [patent_doc_number] => 20080068901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Wordline Booster Circuit and Method of Operating a Wordline Booster Circuit' [patent_app_type] => utility [patent_app_number] => 11/847754 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4648 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20080068901.pdf [firstpage_image] =>[orig_patent_app_number] => 11847754 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847754
Wordline booster circuit and method of operating a wordline booster circuit Aug 29, 2007 Issued
Array ( [id] => 4770366 [patent_doc_number] => 20080056024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'DEVICE AND METHOD FOR READING OUT MEMORY INFORMATION' [patent_app_type] => utility [patent_app_number] => 11/846914 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6834 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20080056024.pdf [firstpage_image] =>[orig_patent_app_number] => 11846914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846914
Device and method for reading out memory information Aug 28, 2007 Issued
Array ( [id] => 4770317 [patent_doc_number] => 20080055975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'METHOD FOR MEASURING THRESHOLD VOLTAGE OF SONOS FLASH DEVICE' [patent_app_type] => utility [patent_app_number] => 11/847030 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20080055975.pdf [firstpage_image] =>[orig_patent_app_number] => 11847030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847030
Method for measuring threshold voltage of SONOS flash device Aug 28, 2007 Issued
Array ( [id] => 5229423 [patent_doc_number] => 20070291530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Separate Write And Read Access Architecture For A Magnetic Tunnel Junction' [patent_app_type] => utility [patent_app_number] => 11/847122 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4950 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20070291530.pdf [firstpage_image] =>[orig_patent_app_number] => 11847122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847122
Separate write and read access architecture for a magnetic tunnel junction Aug 28, 2007 Issued
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