Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5009483 [patent_doc_number] => 20070279961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'PROVIDING A REFERENCE VOLTAGE TO A CROSS POINT MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 11/636735 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20070279961.pdf [firstpage_image] =>[orig_patent_app_number] => 11636735 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636735
Providing a reference voltage to a cross point memory array Dec 10, 2006 Issued
Array ( [id] => 895136 [patent_doc_number] => 07345932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Low power dissipation voltage generator' [patent_app_type] => utility [patent_app_number] => 11/600629 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345932.pdf [firstpage_image] =>[orig_patent_app_number] => 11600629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600629
Low power dissipation voltage generator Nov 15, 2006 Issued
Array ( [id] => 4898082 [patent_doc_number] => 20080117695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS' [patent_app_type] => utility [patent_app_number] => 11/560428 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5964 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20080117695.pdf [firstpage_image] =>[orig_patent_app_number] => 11560428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560428
Delay mechanism for unbalanced read/write paths in domino SRAM arrays Nov 15, 2006 Issued
Array ( [id] => 387521 [patent_doc_number] => 07304892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Flash memory device and method for controlling erase operation of the same' [patent_app_type] => utility [patent_app_number] => 11/594356 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 12494 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304892.pdf [firstpage_image] =>[orig_patent_app_number] => 11594356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/594356
Flash memory device and method for controlling erase operation of the same Nov 5, 2006 Issued
Array ( [id] => 4998602 [patent_doc_number] => 20070041236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Methods and apparatuses for a sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/590695 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20070041236.pdf [firstpage_image] =>[orig_patent_app_number] => 11590695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590695
Methods and apparatuses for a sense amplifier Oct 29, 2006 Issued
Array ( [id] => 357093 [patent_doc_number] => 07489535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Circuit configurations and methods for manufacturing five-volt one time programmable (OTP) memory arrays' [patent_app_type] => utility [patent_app_number] => 11/588736 [patent_app_country] => US [patent_app_date] => 2006-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4416 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489535.pdf [firstpage_image] =>[orig_patent_app_number] => 11588736 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588736
Circuit configurations and methods for manufacturing five-volt one time programmable (OTP) memory arrays Oct 27, 2006 Issued
Array ( [id] => 5031617 [patent_doc_number] => 20070096156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/588328 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096156.pdf [firstpage_image] =>[orig_patent_app_number] => 11588328 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588328
Semiconductor memory device Oct 26, 2006 Issued
Array ( [id] => 5033230 [patent_doc_number] => 20070097769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/586518 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097769.pdf [firstpage_image] =>[orig_patent_app_number] => 11586518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586518
Semiconductor memory Oct 25, 2006 Issued
Array ( [id] => 5033234 [patent_doc_number] => 20070097773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Semiconductor memory device and method of adjusting same' [patent_app_type] => utility [patent_app_number] => 11/585948 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3414 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20070097773.pdf [firstpage_image] =>[orig_patent_app_number] => 11585948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585948
Semiconductor memory device and method of adjusting same Oct 24, 2006 Issued
Array ( [id] => 4902832 [patent_doc_number] => 20080112245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'Bit line dummy core-cell and method for producing a bit line dummy core-cell' [patent_app_type] => utility [patent_app_number] => 11/586176 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20080112245.pdf [firstpage_image] =>[orig_patent_app_number] => 11586176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586176
Bit line dummy core-cell and method for producing a bit line dummy core-cell Oct 24, 2006 Issued
Array ( [id] => 811818 [patent_doc_number] => 07417912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-26 [patent_title] => 'Bit-line sense amplifier driver' [patent_app_type] => utility [patent_app_number] => 11/585096 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3042 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/417/07417912.pdf [firstpage_image] =>[orig_patent_app_number] => 11585096 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585096
Bit-line sense amplifier driver Oct 23, 2006 Issued
Array ( [id] => 367484 [patent_doc_number] => 07480169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Ideal CMOS SRAM system implementation' [patent_app_type] => utility [patent_app_number] => 11/585076 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1877 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 601 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480169.pdf [firstpage_image] =>[orig_patent_app_number] => 11585076 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585076
Ideal CMOS SRAM system implementation Oct 23, 2006 Issued
Array ( [id] => 5078177 [patent_doc_number] => 20070121401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Precharge apparatus' [patent_app_type] => utility [patent_app_number] => 11/584642 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3667 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20070121401.pdf [firstpage_image] =>[orig_patent_app_number] => 11584642 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584642
Precharge apparatus Oct 22, 2006 Issued
Array ( [id] => 895215 [patent_doc_number] => 07345950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Synchronous semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/583980 [patent_app_country] => US [patent_app_date] => 2006-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7414 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/345/07345950.pdf [firstpage_image] =>[orig_patent_app_number] => 11583980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583980
Synchronous semiconductor memory device Oct 19, 2006 Issued
Array ( [id] => 5021193 [patent_doc_number] => 20070147159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit' [patent_app_type] => utility [patent_app_number] => 11/583066 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16224 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20070147159.pdf [firstpage_image] =>[orig_patent_app_number] => 11583066 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583066
Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit Oct 18, 2006 Issued
Array ( [id] => 4987238 [patent_doc_number] => 20070153576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Memory with output control' [patent_app_type] => utility [patent_app_number] => 11/583354 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15400 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153576.pdf [firstpage_image] =>[orig_patent_app_number] => 11583354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583354
Memory with output control Oct 18, 2006 Issued
Array ( [id] => 862615 [patent_doc_number] => 07372753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Two-cycle sensing in a two-terminal memory array having leakage current' [patent_app_type] => utility [patent_app_number] => 11/583676 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 63 [patent_no_of_words] => 25637 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372753.pdf [firstpage_image] =>[orig_patent_app_number] => 11583676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583676
Two-cycle sensing in a two-terminal memory array having leakage current Oct 18, 2006 Issued
Array ( [id] => 854771 [patent_doc_number] => 07379364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Sensing a signal in a two-terminal memory array having leakage current' [patent_app_type] => utility [patent_app_number] => 11/583446 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 63 [patent_no_of_words] => 25485 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/379/07379364.pdf [firstpage_image] =>[orig_patent_app_number] => 11583446 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583446
Sensing a signal in a two-terminal memory array having leakage current Oct 18, 2006 Issued
Array ( [id] => 844919 [patent_doc_number] => 07388791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Signal interface' [patent_app_type] => utility [patent_app_number] => 11/583130 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9731 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/388/07388791.pdf [firstpage_image] =>[orig_patent_app_number] => 11583130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/583130
Signal interface Oct 18, 2006 Issued
Array ( [id] => 5408699 [patent_doc_number] => 20090122597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 12/089090 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122597.pdf [firstpage_image] =>[orig_patent_app_number] => 12089090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/089090
Magnetic random access memory Sep 28, 2006 Issued
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