Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5856446 [patent_doc_number] => 20060227649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Dual port memory cell with reduced coupling capacitance and small cell size' [patent_app_type] => utility [patent_app_number] => 11/403370 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2686 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20060227649.pdf [firstpage_image] =>[orig_patent_app_number] => 11403370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403370
Dual port memory cell with reduced coupling capacitance and small cell size Apr 11, 2006 Issued
Array ( [id] => 854673 [patent_doc_number] => 07379325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Non-imprinting memory with high speed erase' [patent_app_type] => utility [patent_app_number] => 11/402696 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 6068 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/379/07379325.pdf [firstpage_image] =>[orig_patent_app_number] => 11402696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/402696
Non-imprinting memory with high speed erase Apr 11, 2006 Issued
Array ( [id] => 5209330 [patent_doc_number] => 20070247914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Non-Volatile Memory In CMOS Logic Process And Method Of Operation Thereof' [patent_app_type] => utility [patent_app_number] => 11/279382 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7615 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247914.pdf [firstpage_image] =>[orig_patent_app_number] => 11279382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279382
Non-volatile memory in CMOS logic process and method of operation thereof Apr 10, 2006 Issued
Array ( [id] => 5856395 [patent_doc_number] => 20060227609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'NON-VOLATILE MEMORY ELECTRONIC DEVICE WITH NAND STRUCTURE BEING MONOLITHICALLY INTEGRATED ON SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 11/279378 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13068 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20060227609.pdf [firstpage_image] =>[orig_patent_app_number] => 11279378 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279378
Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor Apr 10, 2006 Issued
Array ( [id] => 399233 [patent_doc_number] => 07295472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Integrated electronic non-volatile memory device having nand structure' [patent_app_type] => utility [patent_app_number] => 11/279384 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 13913 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295472.pdf [firstpage_image] =>[orig_patent_app_number] => 11279384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279384
Integrated electronic non-volatile memory device having nand structure Apr 10, 2006 Issued
Array ( [id] => 161353 [patent_doc_number] => 07675788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Electronic non-volatile memory device having a cNAND structure and being monolithically integrated on semiconductor' [patent_app_type] => utility [patent_app_number] => 11/401521 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675788.pdf [firstpage_image] =>[orig_patent_app_number] => 11401521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401521
Electronic non-volatile memory device having a cNAND structure and being monolithically integrated on semiconductor Apr 10, 2006 Issued
Array ( [id] => 5246291 [patent_doc_number] => 20070242525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'METHOD FOR ERASING FLASH MEMORIES AND RELATED SYSTEM THEREOF' [patent_app_type] => utility [patent_app_number] => 11/278964 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4328 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242525.pdf [firstpage_image] =>[orig_patent_app_number] => 11278964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278964
Method for erasing flash memories and related system thereof Apr 6, 2006 Issued
Array ( [id] => 114172 [patent_doc_number] => 07719883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Magnetoresistive element, particularly memory element or logic element, and method for writing information to such an element' [patent_app_type] => utility [patent_app_number] => 11/909854 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4032 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719883.pdf [firstpage_image] =>[orig_patent_app_number] => 11909854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/909854
Magnetoresistive element, particularly memory element or logic element, and method for writing information to such an element Mar 29, 2006 Issued
Array ( [id] => 5665845 [patent_doc_number] => 20060171195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/384242 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12551 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20060171195.pdf [firstpage_image] =>[orig_patent_app_number] => 11384242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/384242
Semiconductor memory device Mar 20, 2006 Issued
Array ( [id] => 5692822 [patent_doc_number] => 20060152968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Spin based device with low transmission barrier' [patent_app_type] => utility [patent_app_number] => 11/373667 [patent_app_country] => US [patent_app_date] => 2006-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9928 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20060152968.pdf [firstpage_image] =>[orig_patent_app_number] => 11373667 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/373667
Spin based device with low transmission barrier Mar 8, 2006 Issued
Array ( [id] => 5618171 [patent_doc_number] => 20060187704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Spin based sensor device' [patent_app_type] => utility [patent_app_number] => 11/369661 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10109 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20060187704.pdf [firstpage_image] =>[orig_patent_app_number] => 11369661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/369661
Spin based sensor device Mar 5, 2006 Issued
Array ( [id] => 883088 [patent_doc_number] => 07355900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Output buffer circuit for semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/360506 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355900.pdf [firstpage_image] =>[orig_patent_app_number] => 11360506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360506
Output buffer circuit for semiconductor memory device Feb 23, 2006 Issued
Array ( [id] => 463489 [patent_doc_number] => 07242622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Methods to resolve hard-to-erase condition in charge trapping non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/359044 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/242/07242622.pdf [firstpage_image] =>[orig_patent_app_number] => 11359044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/359044
Methods to resolve hard-to-erase condition in charge trapping non-volatile memory Feb 21, 2006 Issued
Array ( [id] => 478619 [patent_doc_number] => 07227784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution' [patent_app_type] => utility [patent_app_number] => 11/358206 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7929 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/227/07227784.pdf [firstpage_image] =>[orig_patent_app_number] => 11358206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358206
Nonvolatile semiconductor memory device performing erase operation that creates narrow threshold distribution Feb 21, 2006 Issued
Array ( [id] => 5111688 [patent_doc_number] => 20070195603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Minimizing effects of program disturb in a memory device' [patent_app_type] => utility [patent_app_number] => 11/359104 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3381 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195603.pdf [firstpage_image] =>[orig_patent_app_number] => 11359104 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/359104
Minimizing effects of program disturb in a memory device Feb 21, 2006 Issued
Array ( [id] => 5782370 [patent_doc_number] => 20060203585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Differential read-out circuit for fuse memory cells' [patent_app_type] => utility [patent_app_number] => 11/358374 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5135 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203585.pdf [firstpage_image] =>[orig_patent_app_number] => 11358374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358374
Differential read-out circuit for fuse memory cells Feb 20, 2006 Issued
Array ( [id] => 594744 [patent_doc_number] => 07443761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Loop filtering for fast PLL locking' [patent_app_type] => utility [patent_app_number] => 11/358266 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8479 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443761.pdf [firstpage_image] =>[orig_patent_app_number] => 11358266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358266
Loop filtering for fast PLL locking Feb 20, 2006 Issued
Array ( [id] => 912736 [patent_doc_number] => 07330383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Semiconductor device with a plurality of fuse elements and method for programming the device' [patent_app_type] => utility [patent_app_number] => 11/356262 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/330/07330383.pdf [firstpage_image] =>[orig_patent_app_number] => 11356262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356262
Semiconductor device with a plurality of fuse elements and method for programming the device Feb 16, 2006 Issued
Array ( [id] => 449130 [patent_doc_number] => 07254080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Fuse circuit and electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/355682 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4593 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254080.pdf [firstpage_image] =>[orig_patent_app_number] => 11355682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355682
Fuse circuit and electronic circuit Feb 15, 2006 Issued
Array ( [id] => 831068 [patent_doc_number] => 07400532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'Programming method to reduce gate coupling interference for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/355830 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9419 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/400/07400532.pdf [firstpage_image] =>[orig_patent_app_number] => 11355830 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355830
Programming method to reduce gate coupling interference for non-volatile memory Feb 15, 2006 Issued
Menu