Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 459699 [patent_doc_number] => 07245552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Parallel data path architecture' [patent_app_type] => utility [patent_app_number] => 11/157868 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4956 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245552.pdf [firstpage_image] =>[orig_patent_app_number] => 11157868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157868
Parallel data path architecture Jun 21, 2005 Issued
Array ( [id] => 6976620 [patent_doc_number] => 20050286335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Memory device for reducing leakage current' [patent_app_type] => utility [patent_app_number] => 11/158492 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3186 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20050286335.pdf [firstpage_image] =>[orig_patent_app_number] => 11158492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158492
Memory device for reducing leakage current Jun 21, 2005 Issued
Array ( [id] => 455582 [patent_doc_number] => 07248512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Semiconductor memory device having controller with improved current consumption' [patent_app_type] => utility [patent_app_number] => 11/157834 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2314 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248512.pdf [firstpage_image] =>[orig_patent_app_number] => 11157834 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157834
Semiconductor memory device having controller with improved current consumption Jun 21, 2005 Issued
Array ( [id] => 554439 [patent_doc_number] => 07167397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Apparatus and method for programming a memory array' [patent_app_type] => utility [patent_app_number] => 11/158518 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5680 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/167/07167397.pdf [firstpage_image] =>[orig_patent_app_number] => 11158518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158518
Apparatus and method for programming a memory array Jun 20, 2005 Issued
Array ( [id] => 628412 [patent_doc_number] => 07136318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Semiconductor memory device and circuit layout of dummy cell' [patent_app_type] => utility [patent_app_number] => 11/156706 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136318.pdf [firstpage_image] =>[orig_patent_app_number] => 11156706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156706
Semiconductor memory device and circuit layout of dummy cell Jun 20, 2005 Issued
Array ( [id] => 409922 [patent_doc_number] => 07286417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Low power dissipation voltage generator' [patent_app_type] => utility [patent_app_number] => 11/157648 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3595 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286417.pdf [firstpage_image] =>[orig_patent_app_number] => 11157648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157648
Low power dissipation voltage generator Jun 20, 2005 Issued
Array ( [id] => 610318 [patent_doc_number] => 07151704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/156708 [patent_app_country] => US [patent_app_date] => 2005-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/151/07151704.pdf [firstpage_image] =>[orig_patent_app_number] => 11156708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156708
Semiconductor memory device Jun 20, 2005 Issued
Array ( [id] => 573065 [patent_doc_number] => 07158423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Semiconductor memory device and array internal power voltage generating method thereof' [patent_app_type] => utility [patent_app_number] => 11/158206 [patent_app_country] => US [patent_app_date] => 2005-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6146 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/158/07158423.pdf [firstpage_image] =>[orig_patent_app_number] => 11158206 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158206
Semiconductor memory device and array internal power voltage generating method thereof Jun 19, 2005 Issued
Array ( [id] => 5687105 [patent_doc_number] => 20060285420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-21 [patent_title] => 'Three Dimensional Twisted Bitline Architecture for Multi-Port Memory' [patent_app_type] => utility [patent_app_number] => 11/160302 [patent_app_country] => US [patent_app_date] => 2005-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3689 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20060285420.pdf [firstpage_image] =>[orig_patent_app_number] => 11160302 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160302
Three dimensional twisted bitline architecture for multi-port memory Jun 16, 2005 Issued
Array ( [id] => 5782299 [patent_doc_number] => 20060203550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Flash Memory Device with Improved Erase Function and Method for Controlling Erase Operation of the Same' [patent_app_type] => utility [patent_app_number] => 11/160278 [patent_app_country] => US [patent_app_date] => 2005-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8128 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203550.pdf [firstpage_image] =>[orig_patent_app_number] => 11160278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160278
Flash memory device with improved erase function and method for controlling erase operation of the same Jun 15, 2005 Issued
Array ( [id] => 6965114 [patent_doc_number] => 20050232011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Memory devices with page buffer having dual registers and metod of using the same' [patent_app_type] => utility [patent_app_number] => 11/153638 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7990 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20050232011.pdf [firstpage_image] =>[orig_patent_app_number] => 11153638 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153638
Memory devices with page buffer having dual registers and method of using the same Jun 13, 2005 Issued
Array ( [id] => 644148 [patent_doc_number] => 07123529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Sense amplifier including multiple conduction state field effect transistor' [patent_app_type] => utility [patent_app_number] => 11/160054 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123529.pdf [firstpage_image] =>[orig_patent_app_number] => 11160054 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/160054
Sense amplifier including multiple conduction state field effect transistor Jun 6, 2005 Issued
Array ( [id] => 7109786 [patent_doc_number] => 20050207240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Digital processing device with disparate magnetoelectronic gates' [patent_app_type] => utility [patent_app_number] => 11/138989 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11155 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20050207240.pdf [firstpage_image] =>[orig_patent_app_number] => 11138989 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138989
Digital processing device with disparate magnetoelectronic gates May 25, 2005 Issued
Array ( [id] => 7108973 [patent_doc_number] => 20050206426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Integrated circuit systems and devices having high precision digital delay lines therein' [patent_app_type] => utility [patent_app_number] => 11/134899 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13834 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20050206426.pdf [firstpage_image] =>[orig_patent_app_number] => 11134899 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134899
Integrated circuit systems and devices having high precision digital delay lines therein May 22, 2005 Issued
Array ( [id] => 6957032 [patent_doc_number] => 20050213402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Semiconductor memory device and test method thereof' [patent_app_type] => utility [patent_app_number] => 11/134576 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9051 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20050213402.pdf [firstpage_image] =>[orig_patent_app_number] => 11134576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/134576
Semiconductor memory device and test method thereof May 18, 2005 Issued
Array ( [id] => 768569 [patent_doc_number] => 07009875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Magnetic memory device structure' [patent_app_type] => utility [patent_app_number] => 11/133518 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 10076 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009875.pdf [firstpage_image] =>[orig_patent_app_number] => 11133518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133518
Magnetic memory device structure May 18, 2005 Issued
Array ( [id] => 775982 [patent_doc_number] => 07002826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/126360 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 10835 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002826.pdf [firstpage_image] =>[orig_patent_app_number] => 11126360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126360
Semiconductor memory device May 10, 2005 Issued
Array ( [id] => 357142 [patent_doc_number] => 07489584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'High performance, low-leakage static random access memory (SRAM)' [patent_app_type] => utility [patent_app_number] => 11/126644 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6721 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489584.pdf [firstpage_image] =>[orig_patent_app_number] => 11126644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126644
High performance, low-leakage static random access memory (SRAM) May 10, 2005 Issued
Array ( [id] => 7229797 [patent_doc_number] => 20050255647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Vertical NROM having a storage density of 1 bit per 1F2' [patent_app_type] => utility [patent_app_number] => 11/122764 [patent_app_country] => US [patent_app_date] => 2005-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20050255647.pdf [firstpage_image] =>[orig_patent_app_number] => 11122764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/122764
Vertical NROM having a storage density of 1 bit per 1F2 May 4, 2005 Issued
Array ( [id] => 762007 [patent_doc_number] => 07016223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Magnetoelectronic memory element with inductively coupled write wires' [patent_app_type] => utility [patent_app_number] => 11/120540 [patent_app_country] => US [patent_app_date] => 2005-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4713 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016223.pdf [firstpage_image] =>[orig_patent_app_number] => 11120540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/120540
Magnetoelectronic memory element with inductively coupled write wires May 1, 2005 Issued
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