Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14220717 [patent_doc_number] => 20190122743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/226410 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226410
Semiconductor memory device and operating method thereof for controlling operating voltages Dec 18, 2018 Issued
Array ( [id] => 14919945 [patent_doc_number] => 10431299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor storage device and memory system [patent_app_type] => utility [patent_app_number] => 16/219410 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 36396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219410
Semiconductor storage device and memory system Dec 12, 2018 Issued
Array ( [id] => 15580189 [patent_doc_number] => 10580486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Method of reading data about memory device, method of controlling memory controller, and storage device including memory device and memory controller [patent_app_type] => utility [patent_app_number] => 16/217315 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 11939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217315 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217315
Method of reading data about memory device, method of controlling memory controller, and storage device including memory device and memory controller Dec 11, 2018 Issued
Array ( [id] => 14163543 [patent_doc_number] => 20190108874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/211589 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16211589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/211589
Memory read stability enhancement with short segmented bit line architecture Dec 5, 2018 Issued
Array ( [id] => 15169567 [patent_doc_number] => 10490286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Electrically-rewritable nonvolatile semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/209520 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 10758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209520 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209520
Electrically-rewritable nonvolatile semiconductor memory device Dec 3, 2018 Issued
Array ( [id] => 15547215 [patent_doc_number] => 10573397 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-25 [patent_title] => Parameter tracking for non-volatile memory to avoid over-programming [patent_app_type] => utility [patent_app_number] => 16/209519 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 16684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209519 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209519
Parameter tracking for non-volatile memory to avoid over-programming Dec 3, 2018 Issued
Array ( [id] => 15474765 [patent_doc_number] => 10553265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Memory circuit having tracking circuit including series-connected transistors [patent_app_type] => utility [patent_app_number] => 16/206314 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16206314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/206314
Memory circuit having tracking circuit including series-connected transistors Nov 29, 2018 Issued
Array ( [id] => 15474779 [patent_doc_number] => 10553272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Method of operating a semiconductor device having CAL latency function [patent_app_type] => utility [patent_app_number] => 16/204750 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7513 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204750
Method of operating a semiconductor device having CAL latency function Nov 28, 2018 Issued
Array ( [id] => 15201407 [patent_doc_number] => 10498215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-03 [patent_title] => Voltage regulator with flexible output voltage [patent_app_type] => utility [patent_app_number] => 16/198775 [patent_app_country] => US [patent_app_date] => 2018-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2619 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198775
Voltage regulator with flexible output voltage Nov 21, 2018 Issued
Array ( [id] => 14163527 [patent_doc_number] => 20190108866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => CHARGE SHARING BETWEEN MEMORY CELL PLATES [patent_app_type] => utility [patent_app_number] => 16/188855 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188855 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188855
Charge sharing between memory cell plates using a conductive path Nov 12, 2018 Issued
Array ( [id] => 14238277 [patent_doc_number] => 20190131311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => NONVOLATILE SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/177635 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177635
Nonvolatile semiconductor storage device with cell transistors Oct 31, 2018 Issued
Array ( [id] => 14587317 [patent_doc_number] => 20190221267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING AN ERASE OPERATION IN THE SAME [patent_app_type] => utility [patent_app_number] => 16/176117 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16176117 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/176117
Nonvolatile memory device and method of performing an erase operation in the same Oct 30, 2018 Issued
Array ( [id] => 14999657 [patent_doc_number] => 20190318786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/172333 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16172333 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/172333
STORAGE DEVICE AND METHOD OF OPERATING THE SAME Oct 25, 2018 Abandoned
Array ( [id] => 14237595 [patent_doc_number] => 20190130970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => NONVOLATILE, ELECTRICALLY NON-PROGRAMMABLE MEMORY DEVICE AND MANUFACTORY PROCESS THEREOF [patent_app_type] => utility [patent_app_number] => 16/169763 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169763
Transformed non-reprogrammable memory array devices and methods of manufacture Oct 23, 2018 Issued
Array ( [id] => 15717115 [patent_doc_number] => 20200105325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Defect Injection Structure and Mechanism for Magnetic Memory [patent_app_type] => utility [patent_app_number] => 16/147257 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147257
Defect injection structure and mechanism for magnetic memory Sep 27, 2018 Issued
Array ( [id] => 13832149 [patent_doc_number] => 20190019559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/134573 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134573
Memory device and a method for programming memory cell transistors Sep 17, 2018 Issued
Array ( [id] => 14800731 [patent_doc_number] => 10403374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Reduction of output voltage ripple in booster circuit [patent_app_type] => utility [patent_app_number] => 16/131770 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6277 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16131770 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/131770
Reduction of output voltage ripple in booster circuit Sep 13, 2018 Issued
Array ( [id] => 15388393 [patent_doc_number] => 10535391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 16/124007 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 25748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124007
Semiconductor storage device Sep 5, 2018 Issued
Array ( [id] => 14903725 [patent_doc_number] => 20190295628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/122155 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/122155
Integrated circuit including a plurality of SRAMs Sep 4, 2018 Issued
Array ( [id] => 14024117 [patent_doc_number] => 20190074052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => USING RUNTIME REVERSE ENGINEERING TO OPTIMIZE DRAM REFRESH [patent_app_type] => utility [patent_app_number] => 16/121869 [patent_app_country] => US [patent_app_date] => 2018-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16121869 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/121869
Using runtime reverse engineering to optimize DRAM refresh Sep 4, 2018 Issued
Menu