Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 635965 [patent_doc_number] => 07130219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Electrically word-erasable non-volatile memory device, and biasing method thereof' [patent_app_type] => utility [patent_app_number] => 11/067478 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3646 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130219.pdf [firstpage_image] =>[orig_patent_app_number] => 11067478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067478
Electrically word-erasable non-volatile memory device, and biasing method thereof Feb 24, 2005 Issued
Array ( [id] => 455562 [patent_doc_number] => 07248511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Random access memory including selective activation of select line' [patent_app_type] => utility [patent_app_number] => 11/065196 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 10843 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/248/07248511.pdf [firstpage_image] =>[orig_patent_app_number] => 11065196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065196
Random access memory including selective activation of select line Feb 23, 2005 Issued
Array ( [id] => 631891 [patent_doc_number] => 07133317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Method and apparatus for programming nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/064316 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3993 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133317.pdf [firstpage_image] =>[orig_patent_app_number] => 11064316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064316
Method and apparatus for programming nonvolatile memory Feb 22, 2005 Issued
Array ( [id] => 7189007 [patent_doc_number] => 20050162931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Reference current generator, and method of programming, adjusting and/or operating same' [patent_app_type] => utility [patent_app_number] => 11/061069 [patent_app_country] => US [patent_app_date] => 2005-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11897 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20050162931.pdf [firstpage_image] =>[orig_patent_app_number] => 11061069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061069
Reference current generator, and method of programming, adjusting and/or operating same Feb 17, 2005 Issued
Array ( [id] => 6911328 [patent_doc_number] => 20050175086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Nonvolatile memory device using hybrid switch cell' [patent_app_type] => utility [patent_app_number] => 11/049682 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3998 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20050175086.pdf [firstpage_image] =>[orig_patent_app_number] => 11049682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049682
Nonvolatile memory device using hybrid switch cell Feb 3, 2005 Issued
Array ( [id] => 936187 [patent_doc_number] => 06975537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Source side self boosting technique for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/049802 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8913 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975537.pdf [firstpage_image] =>[orig_patent_app_number] => 11049802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049802
Source side self boosting technique for non-volatile memory Feb 2, 2005 Issued
Array ( [id] => 7096373 [patent_doc_number] => 20050128831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Content addressable memory cell techniques' [patent_app_type] => utility [patent_app_number] => 11/040976 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1643 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128831.pdf [firstpage_image] =>[orig_patent_app_number] => 11040976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040976
Content addressable memory cell techniques Jan 20, 2005 Issued
Array ( [id] => 7604340 [patent_doc_number] => 07116596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method of apparatus for enhanced sensing of low voltage memory' [patent_app_type] => utility [patent_app_number] => 11/038400 [patent_app_country] => US [patent_app_date] => 2005-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3062 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/116/07116596.pdf [firstpage_image] =>[orig_patent_app_number] => 11038400 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038400
Method of apparatus for enhanced sensing of low voltage memory Jan 18, 2005 Issued
Array ( [id] => 665586 [patent_doc_number] => 07102929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout' [patent_app_type] => utility [patent_app_number] => 11/036835 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 20645 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102929.pdf [firstpage_image] =>[orig_patent_app_number] => 11036835 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036835
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Jan 13, 2005 Issued
Array ( [id] => 693371 [patent_doc_number] => 07075826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout' [patent_app_type] => utility [patent_app_number] => 11/036945 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 20640 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075826.pdf [firstpage_image] =>[orig_patent_app_number] => 11036945 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036945
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Jan 13, 2005 Issued
Array ( [id] => 657272 [patent_doc_number] => 07110302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout' [patent_app_type] => utility [patent_app_number] => 11/036868 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 83 [patent_no_of_words] => 20501 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110302.pdf [firstpage_image] =>[orig_patent_app_number] => 11036868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036868
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Jan 13, 2005 Issued
Array ( [id] => 7096347 [patent_doc_number] => 20050128805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout' [patent_app_type] => utility [patent_app_number] => 11/036961 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 20413 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128805.pdf [firstpage_image] =>[orig_patent_app_number] => 11036961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036961
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Jan 13, 2005 Issued
Array ( [id] => 7211406 [patent_doc_number] => 20050259470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Reference sensing circuit' [patent_app_type] => utility [patent_app_number] => 11/026910 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3662 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20050259470.pdf [firstpage_image] =>[orig_patent_app_number] => 11026910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026910
Reference sensing circuit Dec 29, 2004 Issued
Array ( [id] => 585912 [patent_doc_number] => 07460414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/596558 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3248 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/460/07460414.pdf [firstpage_image] =>[orig_patent_app_number] => 10596558 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/596558
Semiconductor device Dec 13, 2004 Issued
Array ( [id] => 6911106 [patent_doc_number] => 20050174864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Voltage regulating circuit and method of regulating voltage' [patent_app_type] => utility [patent_app_number] => 11/008672 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2510 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174864.pdf [firstpage_image] =>[orig_patent_app_number] => 11008672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008672
Voltage regulating circuit and method of regulating voltage Dec 9, 2004 Issued
Array ( [id] => 6916917 [patent_doc_number] => 20050094478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/989372 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11586 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094478.pdf [firstpage_image] =>[orig_patent_app_number] => 10989372 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989372
Method of transferring initially-setting data in a non-volatile semiconductor memory Nov 16, 2004 Issued
Array ( [id] => 674431 [patent_doc_number] => 07092290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'High speed programming system with reduced over programming' [patent_app_type] => utility [patent_app_number] => 10/990702 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 8902 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092290.pdf [firstpage_image] =>[orig_patent_app_number] => 10990702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990702
High speed programming system with reduced over programming Nov 15, 2004 Issued
Array ( [id] => 6989849 [patent_doc_number] => 20050088886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/979124 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11808 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088886.pdf [firstpage_image] =>[orig_patent_app_number] => 10979124 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979124
Semiconductor integrated circuit Nov 2, 2004 Abandoned
Array ( [id] => 426252 [patent_doc_number] => 07272037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Method for programming a multilevel phase change memory device' [patent_app_type] => utility [patent_app_number] => 10/976648 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4720 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272037.pdf [firstpage_image] =>[orig_patent_app_number] => 10976648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/976648
Method for programming a multilevel phase change memory device Oct 28, 2004 Issued
Array ( [id] => 6989866 [patent_doc_number] => 20050088903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Semiconductor memory device of hierarchy word type and sub word driver circuit' [patent_app_type] => utility [patent_app_number] => 10/972486 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8885 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20050088903.pdf [firstpage_image] =>[orig_patent_app_number] => 10972486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/972486
Semiconductor memory device of hierarchy word type and sub word driver circuit Oct 25, 2004 Issued
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