Jon D. Epperson

Array ( [id] => 554120 [patent_doc_number] => 07164611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Data retention kill function' [patent_app_type] => utility [patent_app_number] => 10/973208 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5570 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164611.pdf [firstpage_image] =>[orig_patent_app_number] => 10973208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 754332 [patent_doc_number] => 07023746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'High-speed synchronous memory device' [patent_app_type] => utility [patent_app_number] => 10/972433 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7196 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023746.pdf [firstpage_image] =>[orig_patent_app_number] => 10972433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7172526 [patent_doc_number] => 20050122812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device having sense amplifier driver that controls enabling timing' [patent_app_type] => utility [patent_app_number] => 10/972855 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6490 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122812.pdf [firstpage_image] =>[orig_patent_app_number] => 10972855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 490038 [patent_doc_number] => 07218545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Polymer de-imprint circuit using negative voltage' [patent_app_type] => utility [patent_app_number] => 10/973580 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3636 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218545.pdf [firstpage_image] =>[orig_patent_app_number] => 10973580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5742172 [patent_doc_number] => 20060087897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Memory output data systems and methods with feedback' [patent_app_type] => utility [patent_app_number] => 10/973750 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3849 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087897.pdf [firstpage_image] =>[orig_patent_app_number] => 10973750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7003782 [patent_doc_number] => 20050169095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Bit line discharge control method and circuit for a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/971776 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10027 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20050169095.pdf [firstpage_image] =>[orig_patent_app_number] => 10971776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 517809 [patent_doc_number] => 07196940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method and apparatus for a multiplexed address line driver' [patent_app_type] => utility [patent_app_number] => 10/971394 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5783 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196940.pdf [firstpage_image] =>[orig_patent_app_number] => 10971394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5742148 [patent_doc_number] => 20060087873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEARCH TIMING FOR CAM COMPARE' [patent_app_type] => utility [patent_app_number] => 10/970522 [patent_app_country] => US [patent_app_date] => 2004-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1835 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087873.pdf [firstpage_image] =>[orig_patent_app_number] => 10970522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5812219 [patent_doc_number] => 20060083092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'DYNAMICAL ADAPTATION OF MEMORY SENSE ELECTRONICS' [patent_app_type] => utility [patent_app_number] => 10/970784 [patent_app_country] => US [patent_app_date] => 2004-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5313 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083092.pdf [firstpage_image] =>[orig_patent_app_number] => 10970784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 475580 [patent_doc_number] => 07230873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Forced pulldown of array read bitlines for generating MUX select signals' [patent_app_type] => utility [patent_app_number] => 10/970452 [patent_app_country] => US [patent_app_date] => 2004-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/230/07230873.pdf [firstpage_image] =>[orig_patent_app_number] => 10970452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7157032 [patent_doc_number] => 20050083775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Data interface device for accessing SDRAM' [patent_app_type] => utility [patent_app_number] => 10/969202 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20050083775.pdf [firstpage_image] =>[orig_patent_app_number] => 10969202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 693399 [patent_doc_number] => 07075843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Sense amplifier for mask read only memory' [patent_app_type] => utility [patent_app_number] => 10/968102 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1358 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075843.pdf [firstpage_image] =>[orig_patent_app_number] => 10968102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 537965 [patent_doc_number] => 07184328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'DQS for data from a memory array' [patent_app_type] => utility [patent_app_number] => 10/967768 [patent_app_country] => US [patent_app_date] => 2004-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3586 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/184/07184328.pdf [firstpage_image] =>[orig_patent_app_number] => 10967768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 762050 [patent_doc_number] => 07016231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 10/965785 [patent_app_country] => US [patent_app_date] => 2004-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5497 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016231.pdf [firstpage_image] =>[orig_patent_app_number] => 10965785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 665590 [patent_doc_number] => 07102933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Combined receiver and latch' [patent_app_type] => utility [patent_app_number] => 10/966776 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102933.pdf [firstpage_image] =>[orig_patent_app_number] => 10966776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 758749 [patent_doc_number] => 07020023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/964642 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1902 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020023.pdf [firstpage_image] =>[orig_patent_app_number] => 10964642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 537672 [patent_doc_number] => 07184308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Flash memory devices and methods for programming the same' [patent_app_type] => utility [patent_app_number] => 10/965446 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10258 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/184/07184308.pdf [firstpage_image] =>[orig_patent_app_number] => 10965446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 229842 [patent_doc_number] => 07602659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Memory device having shared fail-repairing circuit capable of repairing row or column fails in memory cell arrays of memory banks' [patent_app_type] => utility [patent_app_number] => 10/965550 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4848 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602659.pdf [firstpage_image] =>[orig_patent_app_number] => 10965550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 741562 [patent_doc_number] => 07035152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'System and method for redundancy memory decoding' [patent_app_type] => utility [patent_app_number] => 10/967064 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7154 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035152.pdf [firstpage_image] =>[orig_patent_app_number] => 10967064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5812201 [patent_doc_number] => 20060083074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Array read access control using MUX select signal gating of the read port' [patent_app_type] => utility [patent_app_number] => 10/965626 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2510 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083074.pdf [firstpage_image] =>[orig_patent_app_number] => 10965626 [rel_patent_id] =>[rel_patent_doc_number] =>)