Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6773223 [patent_doc_number] => 20030016561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Erasing method in non-volatile memory device' [patent_app_type] => new [patent_app_number] => 10/090902 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4292 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20030016561.pdf [firstpage_image] =>[orig_patent_app_number] => 10090902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/090902
Erasing method in non-volatile memory device May 30, 2002 Issued
Array ( [id] => 6700402 [patent_doc_number] => 20030223282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Redundancy circuit and method for semiconductor memory devices' [patent_app_type] => new [patent_app_number] => 10/161501 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4099 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20030223282.pdf [firstpage_image] =>[orig_patent_app_number] => 10161501 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161501
Redundancy circuit and method for semiconductor memory devices May 30, 2002 Issued
Array ( [id] => 1108148 [patent_doc_number] => 06813182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Diode-and-fuse memory elements for a write-once memory comprising an anisotropic semiconductor sheet' [patent_app_type] => B2 [patent_app_number] => 10/160802 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3596 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813182.pdf [firstpage_image] =>[orig_patent_app_number] => 10160802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/160802
Diode-and-fuse memory elements for a write-once memory comprising an anisotropic semiconductor sheet May 30, 2002 Issued
Array ( [id] => 1191134 [patent_doc_number] => 06735126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 10/155997 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5228 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735126.pdf [firstpage_image] =>[orig_patent_app_number] => 10155997 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155997
Semiconductor memory May 28, 2002 Issued
Array ( [id] => 6820752 [patent_doc_number] => 20030218913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Stepped pre-erase voltages for mirrorbit erase' [patent_app_type] => new [patent_app_number] => 10/155767 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4632 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218913.pdf [firstpage_image] =>[orig_patent_app_number] => 10155767 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155767
Stepped pre-erase voltages for mirrorbit erase May 23, 2002 Abandoned
Array ( [id] => 1158440 [patent_doc_number] => 06771555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Row access information transfer device using internal wiring of a memory cell array' [patent_app_type] => B2 [patent_app_number] => 10/152705 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2802 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/771/06771555.pdf [firstpage_image] =>[orig_patent_app_number] => 10152705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152705
Row access information transfer device using internal wiring of a memory cell array May 21, 2002 Issued
Array ( [id] => 1180225 [patent_doc_number] => 06751129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Efficient read, write methods for multi-state memory' [patent_app_type] => B1 [patent_app_number] => 10/152536 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9286 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751129.pdf [firstpage_image] =>[orig_patent_app_number] => 10152536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152536
Efficient read, write methods for multi-state memory May 20, 2002 Issued
Array ( [id] => 1220078 [patent_doc_number] => 06707738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Semiconductor memory device having mesh-type structure of precharge voltage line' [patent_app_type] => B2 [patent_app_number] => 10/145001 [patent_app_country] => US [patent_app_date] => 2002-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4757 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707738.pdf [firstpage_image] =>[orig_patent_app_number] => 10145001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/145001
Semiconductor memory device having mesh-type structure of precharge voltage line May 13, 2002 Issued
Array ( [id] => 1191138 [patent_doc_number] => 06735130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'Differential voltage memory bus' [patent_app_type] => B2 [patent_app_number] => 10/146506 [patent_app_country] => US [patent_app_date] => 2002-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2399 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735130.pdf [firstpage_image] =>[orig_patent_app_number] => 10146506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146506
Differential voltage memory bus May 13, 2002 Issued
Array ( [id] => 6695732 [patent_doc_number] => 20030107926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Semiconductor device provided with memory chips' [patent_app_type] => new [patent_app_number] => 10/140104 [patent_app_country] => US [patent_app_date] => 2002-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9744 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107926.pdf [firstpage_image] =>[orig_patent_app_number] => 10140104 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140104
Semiconductor device provided with memory chips May 7, 2002 Issued
Array ( [id] => 6800268 [patent_doc_number] => 20030095432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Nonvolatile semiconductor memory device capable of writing multilevel data at high rate' [patent_app_type] => new [patent_app_number] => 10/140105 [patent_app_country] => US [patent_app_date] => 2002-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8799 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20030095432.pdf [firstpage_image] =>[orig_patent_app_number] => 10140105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140105
Nonvolatile semiconductor memory device capable of writing multilevel data at high rate May 7, 2002 Issued
Array ( [id] => 6046095 [patent_doc_number] => 20020167853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/140803 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8474 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167853.pdf [firstpage_image] =>[orig_patent_app_number] => 10140803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140803
Readable semiconductor memory device May 6, 2002 Issued
Array ( [id] => 6422832 [patent_doc_number] => 20020126520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/139330 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9685 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126520.pdf [firstpage_image] =>[orig_patent_app_number] => 10139330 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139330
Semiconductor device May 6, 2002 Issued
Array ( [id] => 1319291 [patent_doc_number] => 06614702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Semiconductor memory devices and methods including coupling and/or floating isolation control signal lines' [patent_app_type] => B2 [patent_app_number] => 10/136606 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7102 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614702.pdf [firstpage_image] =>[orig_patent_app_number] => 10136606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136606
Semiconductor memory devices and methods including coupling and/or floating isolation control signal lines Apr 30, 2002 Issued
Array ( [id] => 6777610 [patent_doc_number] => 20030048691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Semiconductor memory device that operates in synchronization with a clock signal' [patent_app_type] => new [patent_app_number] => 10/135507 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8476 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20030048691.pdf [firstpage_image] =>[orig_patent_app_number] => 10135507 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135507
Semiconductor memory device that operates in synchronization with a clock signal Apr 30, 2002 Issued
Array ( [id] => 1268874 [patent_doc_number] => 06661695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Capacitance sensing technique for ferroelectric random access memory arrays' [patent_app_type] => B2 [patent_app_number] => 10/136477 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3301 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661695.pdf [firstpage_image] =>[orig_patent_app_number] => 10136477 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136477
Capacitance sensing technique for ferroelectric random access memory arrays Apr 30, 2002 Issued
Array ( [id] => 6371838 [patent_doc_number] => 20020118587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => ' Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/134521 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9149 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118587.pdf [firstpage_image] =>[orig_patent_app_number] => 10134521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/134521
Semiconductor memory including a circuit for selecting redundant memory cells Apr 29, 2002 Issued
Array ( [id] => 1520423 [patent_doc_number] => 06501680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Nonvolatile memory, cell array thereof, and method for sensing data therefrom' [patent_app_type] => B1 [patent_app_number] => 10/126584 [patent_app_country] => US [patent_app_date] => 2002-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6768 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501680.pdf [firstpage_image] =>[orig_patent_app_number] => 10126584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/126584
Nonvolatile memory, cell array thereof, and method for sensing data therefrom Apr 21, 2002 Issued
Array ( [id] => 1227311 [patent_doc_number] => 06700815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Refresh scheme for dynamic page programming' [patent_app_type] => B2 [patent_app_number] => 10/119273 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4070 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700815.pdf [firstpage_image] =>[orig_patent_app_number] => 10119273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/119273
Refresh scheme for dynamic page programming Apr 7, 2002 Issued
Array ( [id] => 704710 [patent_doc_number] => 07064987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Memory address generator with scheduled write and read address generating capability' [patent_app_type] => utility [patent_app_number] => 10/117029 [patent_app_country] => US [patent_app_date] => 2002-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3131 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064987.pdf [firstpage_image] =>[orig_patent_app_number] => 10117029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117029
Memory address generator with scheduled write and read address generating capability Apr 3, 2002 Issued
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