Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13950337 [patent_doc_number] => 10210947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Multi-port memory, semiconductor device, and memory macro-cell capable of performing test in a distributed state [patent_app_type] => utility [patent_app_number] => 15/947075 [patent_app_country] => US [patent_app_date] => 2018-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10263 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947075 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/947075
Multi-port memory, semiconductor device, and memory macro-cell capable of performing test in a distributed state Apr 5, 2018 Issued
Array ( [id] => 13995181 [patent_doc_number] => 20190066748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MEMORY DEVICES CONFIGURED TO PREVENT READ FAILURE DUE TO LEAKAGE CURRENT INTO BIT LINE [patent_app_type] => utility [patent_app_number] => 15/946055 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946055
Memory devices configured to prevent read failure due to leakage current into bit line Apr 4, 2018 Issued
Array ( [id] => 13527879 [patent_doc_number] => 20180315482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => SENSING CIRCUIT FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/942837 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942837 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942837
Sensing circuit with voltage clamp for non-volatile memory Apr 1, 2018 Issued
Array ( [id] => 13334463 [patent_doc_number] => 20180218769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => WRITE ASSIST CIRCUIT FOR LOWERING A MEMORY SUPPLY VOLTAGE AND COUPLING A MEMORY BIT LINE [patent_app_type] => utility [patent_app_number] => 15/940800 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940800 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940800
Write assist circuit for lowering a memory supply voltage and coupling a memory bit line Mar 28, 2018 Issued
Array ( [id] => 14011247 [patent_doc_number] => 10224098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Non-volatile memory device [patent_app_type] => utility [patent_app_number] => 15/937937 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 15434 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/937937
Non-volatile memory device Mar 27, 2018 Issued
Array ( [id] => 14737957 [patent_doc_number] => 10388387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Memory system and operating method of memory system [patent_app_type] => utility [patent_app_number] => 15/927127 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 18477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927127 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/927127
Memory system and operating method of memory system Mar 20, 2018 Issued
Array ( [id] => 13666611 [patent_doc_number] => 10163476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Method of operating tracking circuit [patent_app_type] => utility [patent_app_number] => 15/923476 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923476
Method of operating tracking circuit Mar 15, 2018 Issued
Array ( [id] => 13306171 [patent_doc_number] => 20180204622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/923282 [patent_app_country] => US [patent_app_date] => 2018-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15923282 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/923282
Non-volatile semiconductor memory device and memory system Mar 15, 2018 Issued
Array ( [id] => 14011263 [patent_doc_number] => 10224106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Method of controlling programming of a three dimensional stacked nonvolatile semiconductor memory [patent_app_type] => utility [patent_app_number] => 15/916332 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 9711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916332
Method of controlling programming of a three dimensional stacked nonvolatile semiconductor memory Mar 8, 2018 Issued
Array ( [id] => 12917320 [patent_doc_number] => 20180197616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/915129 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915129 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915129
Nonvolatile semiconductor memory device Mar 7, 2018 Issued
Array ( [id] => 16624610 [patent_doc_number] => 20210043263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => PERFORMING READ OPERATION PRIOR TO TWO-PASS PROGRAMMING OF STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/636309 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/636309
Performing read operation prior to two-pass programming of storage system Mar 6, 2018 Issued
Array ( [id] => 12917275 [patent_doc_number] => 20180197601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/911824 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911824 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911824
Memory read stability enhancement with short segmented bit line architecture Mar 4, 2018 Issued
Array ( [id] => 14366417 [patent_doc_number] => 10304520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => High signal voltage tolerance in single-ended memory interface [patent_app_type] => utility [patent_app_number] => 15/886955 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886955 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886955
High signal voltage tolerance in single-ended memory interface Feb 1, 2018 Issued
Array ( [id] => 12848431 [patent_doc_number] => 20180174650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => ONE-TIME PROGRAMMABLE DEVICES USING FINFET STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/884362 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884362
One-time programmable devices having a semiconductor fin structure with a divided active region Jan 29, 2018 Issued
Array ( [id] => 14800679 [patent_doc_number] => 10403347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Apparatuses and methods for accessing ferroelectric memory including providing reference voltage level [patent_app_type] => utility [patent_app_number] => 15/882881 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7386 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882881
Apparatuses and methods for accessing ferroelectric memory including providing reference voltage level Jan 28, 2018 Issued
Array ( [id] => 14252073 [patent_doc_number] => 10276243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Semiconductor memory device and writing operation method thereof in which first memory cells of a page that are in a first group of contiguous columns are programmed and verified separately from second memory cells of the same page that are in a second group of contiguous columns that does not overlap with the first group [patent_app_type] => utility [patent_app_number] => 15/876713 [patent_app_country] => US [patent_app_date] => 2018-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 14131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15876713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/876713
Semiconductor memory device and writing operation method thereof in which first memory cells of a page that are in a first group of contiguous columns are programmed and verified separately from second memory cells of the same page that are in a second group of contiguous columns that does not overlap with the first group Jan 21, 2018 Issued
Array ( [id] => 12758848 [patent_doc_number] => 20180144784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SEMICONDUCTOR DEVICE HAVING CAL LATENCY FUNCTION [patent_app_type] => utility [patent_app_number] => 15/875574 [patent_app_country] => US [patent_app_date] => 2018-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15875574 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/875574
System, method, and controller for supplying address and command signals after a chip select signal Jan 18, 2018 Issued
Array ( [id] => 13832141 [patent_doc_number] => 20190019555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/873069 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873069 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873069
Semiconductor memory device for performing coding program and operating method thereof Jan 16, 2018 Issued
Array ( [id] => 12416304 [patent_doc_number] => 09972381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-15 [patent_title] => Memory with output control [patent_app_type] => utility [patent_app_number] => 15/868219 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 15441 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868219
Memory with output control Jan 10, 2018 Issued
Array ( [id] => 13893091 [patent_doc_number] => 10199097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure [patent_app_type] => utility [patent_app_number] => 15/855671 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855671 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855671
Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure Dec 26, 2017 Issued
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