Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1334730 [patent_doc_number] => 06600688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Semiconductor memory and method of operating the same' [patent_app_type] => B2 [patent_app_number] => 09/964508 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10038 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600688.pdf [firstpage_image] =>[orig_patent_app_number] => 09964508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964508
Semiconductor memory and method of operating the same Sep 27, 2001 Issued
Array ( [id] => 5934653 [patent_doc_number] => 20020060935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Defective address storage scheme for memory device' [patent_app_type] => new [patent_app_number] => 09/967102 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3715 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060935.pdf [firstpage_image] =>[orig_patent_app_number] => 09967102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967102
Defective address storage scheme for memory device Sep 27, 2001 Issued
Array ( [id] => 1426304 [patent_doc_number] => 06510099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Memory control with dynamic driver disabling' [patent_app_type] => B1 [patent_app_number] => 09/966580 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4950 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510099.pdf [firstpage_image] =>[orig_patent_app_number] => 09966580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966580
Memory control with dynamic driver disabling Sep 27, 2001 Issued
Array ( [id] => 1585318 [patent_doc_number] => 06424564 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'MRAM architectures for increased write selectivity' [patent_app_type] => B1 [patent_app_number] => 09/964217 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5038 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424564.pdf [firstpage_image] =>[orig_patent_app_number] => 09964217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964217
MRAM architectures for increased write selectivity Sep 25, 2001 Issued
Array ( [id] => 6673095 [patent_doc_number] => 20030058698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Memory with high performance unit architecture' [patent_app_type] => new [patent_app_number] => 09/964207 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1387 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20030058698.pdf [firstpage_image] =>[orig_patent_app_number] => 09964207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964207
Memory with high performance unit architecture Sep 25, 2001 Abandoned
Array ( [id] => 1427120 [patent_doc_number] => 06522574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'MRAM architectures for increased write selectivity' [patent_app_type] => B2 [patent_app_number] => 09/964218 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5053 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522574.pdf [firstpage_image] =>[orig_patent_app_number] => 09964218 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964218
MRAM architectures for increased write selectivity Sep 24, 2001 Issued
Array ( [id] => 6239856 [patent_doc_number] => 20020044478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Integrated memory having memory cells that each include a ferroelectric memory transistor' [patent_app_type] => new [patent_app_number] => 09/963007 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3195 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20020044478.pdf [firstpage_image] =>[orig_patent_app_number] => 09963007 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963007
Integrated memory having memory cells that each include a ferroelectric memory transistor Sep 24, 2001 Issued
Array ( [id] => 1470030 [patent_doc_number] => 06459626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Integrated memory having memory cells and reference cells, and corresponding operating method' [patent_app_type] => B1 [patent_app_number] => 09/962703 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4593 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459626.pdf [firstpage_image] =>[orig_patent_app_number] => 09962703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962703
Integrated memory having memory cells and reference cells, and corresponding operating method Sep 23, 2001 Issued
Array ( [id] => 5934677 [patent_doc_number] => 20020060948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Clock device for supporting multiplicity of memory module types' [patent_app_type] => new [patent_app_number] => 09/955781 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060948.pdf [firstpage_image] =>[orig_patent_app_number] => 09955781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955781
Clock device for supporting multiplicity of memory module types Sep 18, 2001 Issued
Array ( [id] => 5934672 [patent_doc_number] => 20020060943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Semiconductor device having early operation high voltage generator and high voltage supplying method therefore' [patent_app_type] => new [patent_app_number] => 09/953202 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4830 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060943.pdf [firstpage_image] =>[orig_patent_app_number] => 09953202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953202
Semiconductor device having early operation high voltage generator and high voltage supplying method therefor Sep 16, 2001 Issued
Array ( [id] => 1431720 [patent_doc_number] => 06504773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Memory testing method and memory testing apparatus' [patent_app_type] => B2 [patent_app_number] => 09/952804 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 15310 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504773.pdf [firstpage_image] =>[orig_patent_app_number] => 09952804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952804
Memory testing method and memory testing apparatus Sep 12, 2001 Issued
Array ( [id] => 6078382 [patent_doc_number] => 20020080653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method for preventing over-erasing of memory cells and flash memory device using the same' [patent_app_type] => new [patent_app_number] => 09/952807 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5444 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20020080653.pdf [firstpage_image] =>[orig_patent_app_number] => 09952807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952807
Method for preventing over-erasing of memory cells and flash memory device using the same Sep 12, 2001 Issued
Array ( [id] => 1406669 [patent_doc_number] => 06549448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'FeRAM having adjacent memory cells sharing cell plate and driving method for the same' [patent_app_type] => B2 [patent_app_number] => 09/949080 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4589 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549448.pdf [firstpage_image] =>[orig_patent_app_number] => 09949080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949080
FeRAM having adjacent memory cells sharing cell plate and driving method for the same Sep 9, 2001 Issued
Array ( [id] => 7611881 [patent_doc_number] => 06903958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Method of writing to an organic memory' [patent_app_type] => utility [patent_app_number] => 10/380206 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903958.pdf [firstpage_image] =>[orig_patent_app_number] => 10380206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/380206
Method of writing to an organic memory Sep 4, 2001 Issued
Array ( [id] => 5933385 [patent_doc_number] => 20020060337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Nonvolatile memory, cell array thereof , and method for sensing data therefrom' [patent_app_type] => new [patent_app_number] => 09/942541 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6787 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20020060337.pdf [firstpage_image] =>[orig_patent_app_number] => 09942541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942541
Nonvolatile memory, cell array thereof, and method for sensing data therefrom Aug 30, 2001 Issued
Array ( [id] => 1303767 [patent_doc_number] => 06628561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Small anti-fuse circuit to facilitate parallel fuse blowing' [patent_app_type] => B2 [patent_app_number] => 09/941602 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3632 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628561.pdf [firstpage_image] =>[orig_patent_app_number] => 09941602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941602
Small anti-fuse circuit to facilitate parallel fuse blowing Aug 29, 2001 Issued
Array ( [id] => 6078423 [patent_doc_number] => 20020080673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Semiconductor configuration with optimized refresh cycle' [patent_app_type] => new [patent_app_number] => 09/941902 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1774 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20020080673.pdf [firstpage_image] =>[orig_patent_app_number] => 09941902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941902
Semiconductor configuration with optimized refresh cycle Aug 28, 2001 Issued
Array ( [id] => 5997073 [patent_doc_number] => 20020027233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => ' Semiconductor device, microcomputer and flash memory' [patent_app_type] => new [patent_app_number] => 09/939708 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18831 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027233.pdf [firstpage_image] =>[orig_patent_app_number] => 09939708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939708
Semiconductor device, microcomputer and flash memory Aug 27, 2001 Issued
Array ( [id] => 1426265 [patent_doc_number] => 06510094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Method and apparatus for refreshing semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 09/940909 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510094.pdf [firstpage_image] =>[orig_patent_app_number] => 09940909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940909
Method and apparatus for refreshing semiconductor memory Aug 27, 2001 Issued
Array ( [id] => 1416559 [patent_doc_number] => 06538911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Content addressable memory with block select for power management' [patent_app_type] => B1 [patent_app_number] => 09/938980 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5879 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538911.pdf [firstpage_image] =>[orig_patent_app_number] => 09938980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938980
Content addressable memory with block select for power management Aug 23, 2001 Issued
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