Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7064211 [patent_doc_number] => 20010043497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'SRAM device' [patent_app_type] => new [patent_app_number] => 09/823102 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6731 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043497.pdf [firstpage_image] =>[orig_patent_app_number] => 09823102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823102
SRAM device Mar 29, 2001 Issued
Array ( [id] => 6882145 [patent_doc_number] => 20010048617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/818509 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11888 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048617.pdf [firstpage_image] =>[orig_patent_app_number] => 09818509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818509
Semiconductor integrated circuit Mar 27, 2001 Issued
Array ( [id] => 6893541 [patent_doc_number] => 20010015907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Negative resistance memory cell and method' [patent_app_type] => new [patent_app_number] => 09/819259 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6655 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015907.pdf [firstpage_image] =>[orig_patent_app_number] => 09819259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819259
Negative resistance memory cell and method Mar 26, 2001 Issued
Array ( [id] => 6395776 [patent_doc_number] => 20020181291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Semiconductor device having reduced leakage and method of operating the same' [patent_app_type] => new [patent_app_number] => 09/813806 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181291.pdf [firstpage_image] =>[orig_patent_app_number] => 09813806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813806
Semiconductor device having reduced leakage and method of operating the same Mar 21, 2001 Issued
Array ( [id] => 6888926 [patent_doc_number] => 20010024381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Current sense amplifier circuit' [patent_app_type] => new [patent_app_number] => 09/796806 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5925 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024381.pdf [firstpage_image] =>[orig_patent_app_number] => 09796806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796806
Current sense amplifier circuit Mar 1, 2001 Issued
Array ( [id] => 1520418 [patent_doc_number] => 06501678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Magnetic systems with irreversible characteristics and a method of manufacturing and repairing and operating such systems' [patent_app_type] => B1 [patent_app_number] => 09/763206 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 9319 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501678.pdf [firstpage_image] =>[orig_patent_app_number] => 09763206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/763206
Magnetic systems with irreversible characteristics and a method of manufacturing and repairing and operating such systems Feb 15, 2001 Issued
Array ( [id] => 1454307 [patent_doc_number] => 06456523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Ferromagnetic double quantum well tunnel magneto-resistance device' [patent_app_type] => B1 [patent_app_number] => 09/762804 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6969 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456523.pdf [firstpage_image] =>[orig_patent_app_number] => 09762804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/762804
Ferromagnetic double quantum well tunnel magneto-resistance device Feb 12, 2001 Issued
Array ( [id] => 1564328 [patent_doc_number] => 06438060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of reducing standby current during power down mode' [patent_app_type] => B1 [patent_app_number] => 09/780606 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438060.pdf [firstpage_image] =>[orig_patent_app_number] => 09780606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780606
Method of reducing standby current during power down mode Feb 11, 2001 Issued
Array ( [id] => 1531189 [patent_doc_number] => 06480429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Shared redundancy for memory having column addressing' [patent_app_type] => B2 [patent_app_number] => 09/781808 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4804 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480429.pdf [firstpage_image] =>[orig_patent_app_number] => 09781808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/781808
Shared redundancy for memory having column addressing Feb 11, 2001 Issued
Array ( [id] => 1256062 [patent_doc_number] => 06671207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Piggyback programming with staircase verify for multi-level cell flash memory designs' [patent_app_type] => B1 [patent_app_number] => 09/779884 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5018 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671207.pdf [firstpage_image] =>[orig_patent_app_number] => 09779884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779884
Piggyback programming with staircase verify for multi-level cell flash memory designs Feb 7, 2001 Issued
Array ( [id] => 6272732 [patent_doc_number] => 20020105846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'HIGH SPEED DRAM LOCAL BIT LINE SENSE AMPLIFIER' [patent_app_type] => new [patent_app_number] => 09/777004 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4139 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105846.pdf [firstpage_image] =>[orig_patent_app_number] => 09777004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777004
High speed DRAM local bit line sense amplifier Feb 6, 2001 Issued
Array ( [id] => 7646436 [patent_doc_number] => 06477084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'NROM cell with improved programming, erasing and cycling' [patent_app_type] => B2 [patent_app_number] => 09/778502 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 6032 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477084.pdf [firstpage_image] =>[orig_patent_app_number] => 09778502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778502
NROM cell with improved programming, erasing and cycling Feb 6, 2001 Issued
Array ( [id] => 1319872 [patent_doc_number] => 06611472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Memory circuit for preventing rise of cell array power source' [patent_app_type] => B2 [patent_app_number] => 09/776909 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6088 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611472.pdf [firstpage_image] =>[orig_patent_app_number] => 09776909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776909
Memory circuit for preventing rise of cell array power source Feb 5, 2001 Issued
Array ( [id] => 6960443 [patent_doc_number] => 20010012214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Semiconductor memory device' [patent_app_type] => new [patent_app_number] => 09/773606 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8899 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012214.pdf [firstpage_image] =>[orig_patent_app_number] => 09773606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773606
Semiconductor memory device Feb 1, 2001 Issued
Array ( [id] => 6907886 [patent_doc_number] => 20010010653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'Semiconductor integrated circuit and method for adjusting characteristics of the same' [patent_app_type] => new [patent_app_number] => 09/773002 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6490 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010653.pdf [firstpage_image] =>[orig_patent_app_number] => 09773002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/773002
Semiconductor integrated circuit and method for adjusting characteristics of the same Jan 30, 2001 Issued
Array ( [id] => 6691720 [patent_doc_number] => 20030039152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'It flash memory recovery scheme for over-erasure' [patent_app_type] => new [patent_app_number] => 09/771808 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1280 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20030039152.pdf [firstpage_image] =>[orig_patent_app_number] => 09771808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771808
It flash memory recovery scheme for over-erasure Jan 28, 2001 Abandoned
Array ( [id] => 1397927 [patent_doc_number] => 06556469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'System and method for multilevel DRAM sensing and restoring' [patent_app_type] => B2 [patent_app_number] => 09/768006 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 5007 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556469.pdf [firstpage_image] =>[orig_patent_app_number] => 09768006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768006
System and method for multilevel DRAM sensing and restoring Jan 23, 2001 Issued
Array ( [id] => 6895707 [patent_doc_number] => 20010026497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method and system for accessing rows in multiple memory banks within an integrated circuit' [patent_app_type] => new [patent_app_number] => 09/769010 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16878 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026497.pdf [firstpage_image] =>[orig_patent_app_number] => 09769010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769010
Method and system for accessing rows in multiple memory banks within an integrated circuit Jan 22, 2001 Issued
Array ( [id] => 6907888 [patent_doc_number] => 20010010655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'Method and system for accessing rows in multiple memory banks within an integrated circuit' [patent_app_type] => new [patent_app_number] => 09/769027 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16869 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010655.pdf [firstpage_image] =>[orig_patent_app_number] => 09769027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769027
Method and system for accessing rows in multiple memory banks within an integrated circuit Jan 22, 2001 Issued
Array ( [id] => 1585295 [patent_doc_number] => 06424558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-23 [patent_title] => 'Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines' [patent_app_type] => B2 [patent_app_number] => 09/767804 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4256 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424558.pdf [firstpage_image] =>[orig_patent_app_number] => 09767804 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767804
Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines Jan 21, 2001 Issued
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