Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1582458 [patent_doc_number] => 06449183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Ferroelectric memory system and method of driving the same' [patent_app_type] => B1 [patent_app_number] => 09/717254 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 11929 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449183.pdf [firstpage_image] =>[orig_patent_app_number] => 09717254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717254
Ferroelectric memory system and method of driving the same Nov 21, 2000 Issued
Array ( [id] => 1538421 [patent_doc_number] => 06337811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor device having semiconductor element becomes operable when connected to external power source' [patent_app_type] => B1 [patent_app_number] => 09/700802 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6455 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337811.pdf [firstpage_image] =>[orig_patent_app_number] => 09700802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/700802
Semiconductor device having semiconductor element becomes operable when connected to external power source Nov 19, 2000 Issued
Array ( [id] => 1437724 [patent_doc_number] => 06356508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Semiconductor storage device' [patent_app_type] => B1 [patent_app_number] => 09/715304 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6831 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356508.pdf [firstpage_image] =>[orig_patent_app_number] => 09715304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715304
Semiconductor storage device Nov 15, 2000 Issued
Array ( [id] => 4393382 [patent_doc_number] => 06304500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Integrated circuit memory devices having data input and output lines extending in the column direction, and circuits and methods for repairing faulty cells' [patent_app_type] => 1 [patent_app_number] => 9/713107 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6075 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304500.pdf [firstpage_image] =>[orig_patent_app_number] => 713107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713107
Integrated circuit memory devices having data input and output lines extending in the column direction, and circuits and methods for repairing faulty cells Nov 14, 2000 Issued
Array ( [id] => 1536897 [patent_doc_number] => 06411554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'High voltage switch circuit having transistors and semiconductor memory device provided with the same' [patent_app_type] => B1 [patent_app_number] => 09/710909 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 13294 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411554.pdf [firstpage_image] =>[orig_patent_app_number] => 09710909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/710909
High voltage switch circuit having transistors and semiconductor memory device provided with the same Nov 13, 2000 Issued
Array ( [id] => 1473342 [patent_doc_number] => 06407961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Dual access memory array' [patent_app_type] => B1 [patent_app_number] => 09/709401 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5660 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407961.pdf [firstpage_image] =>[orig_patent_app_number] => 09709401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709401
Dual access memory array Nov 12, 2000 Issued
Array ( [id] => 1396464 [patent_doc_number] => 06560160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Multi-port memory that sequences port accesses' [patent_app_type] => B1 [patent_app_number] => 09/712409 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2606 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560160.pdf [firstpage_image] =>[orig_patent_app_number] => 09712409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712409
Multi-port memory that sequences port accesses Nov 12, 2000 Issued
Array ( [id] => 7644646 [patent_doc_number] => 06473327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Semiconductor memory having a pair of bank select drivers driving each bank select line' [patent_app_type] => B1 [patent_app_number] => 09/709204 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4293 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473327.pdf [firstpage_image] =>[orig_patent_app_number] => 09709204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/709204
Semiconductor memory having a pair of bank select drivers driving each bank select line Nov 8, 2000 Issued
Array ( [id] => 1431746 [patent_doc_number] => 06504786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'High speed, scalable, dynamic integrated programmable switch (DIPS) device' [patent_app_type] => B1 [patent_app_number] => 09/707606 [patent_app_country] => US [patent_app_date] => 2000-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 6470 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504786.pdf [firstpage_image] =>[orig_patent_app_number] => 09707606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/707606
High speed, scalable, dynamic integrated programmable switch (DIPS) device Nov 6, 2000 Issued
Array ( [id] => 1565144 [patent_doc_number] => 06363004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Nonvolatile ferroelectric memory having shunt lines' [patent_app_type] => B1 [patent_app_number] => 09/697502 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 41 [patent_no_of_words] => 9684 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363004.pdf [firstpage_image] =>[orig_patent_app_number] => 09697502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697502
Nonvolatile ferroelectric memory having shunt lines Oct 26, 2000 Issued
Array ( [id] => 1555078 [patent_doc_number] => 06400607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Reading circuit for a non-volatile memory' [patent_app_type] => B1 [patent_app_number] => 09/699304 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400607.pdf [firstpage_image] =>[orig_patent_app_number] => 09699304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699304
Reading circuit for a non-volatile memory Oct 26, 2000 Issued
Array ( [id] => 1461080 [patent_doc_number] => 06426891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Nonvolatile memory with a two-terminal switching element and its driving method' [patent_app_type] => B1 [patent_app_number] => 09/697207 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6498 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426891.pdf [firstpage_image] =>[orig_patent_app_number] => 09697207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697207
Nonvolatile memory with a two-terminal switching element and its driving method Oct 25, 2000 Issued
Array ( [id] => 4346419 [patent_doc_number] => 06333890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Memory device with a plurality of common data buses' [patent_app_type] => 1 [patent_app_number] => 9/695302 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5742 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333890.pdf [firstpage_image] =>[orig_patent_app_number] => 695302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/695302
Memory device with a plurality of common data buses Oct 24, 2000 Issued
Array ( [id] => 1552318 [patent_doc_number] => 06347064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Synchronous mask ROM device operable in consecutive read operation' [patent_app_type] => B1 [patent_app_number] => 09/694103 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5353 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347064.pdf [firstpage_image] =>[orig_patent_app_number] => 09694103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/694103
Synchronous mask ROM device operable in consecutive read operation Oct 18, 2000 Issued
Array ( [id] => 1398576 [patent_doc_number] => 06556501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations' [patent_app_type] => B1 [patent_app_number] => 09/690934 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7380 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556501.pdf [firstpage_image] =>[orig_patent_app_number] => 09690934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690934
Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations Oct 16, 2000 Issued
Array ( [id] => 4342240 [patent_doc_number] => 06320817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Tri-stating address input circuit' [patent_app_type] => 1 [patent_app_number] => 9/685179 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2197 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320817.pdf [firstpage_image] =>[orig_patent_app_number] => 685179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685179
Tri-stating address input circuit Oct 10, 2000 Issued
Array ( [id] => 1429189 [patent_doc_number] => 06515885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Tri-stating address input circuit' [patent_app_type] => B1 [patent_app_number] => 09/685721 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2242 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515885.pdf [firstpage_image] =>[orig_patent_app_number] => 09685721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685721
Tri-stating address input circuit Oct 10, 2000 Issued
Array ( [id] => 4336681 [patent_doc_number] => 06313501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Nonvolatile memory, cell array thereof, and method for sensing data therefrom' [patent_app_type] => 1 [patent_app_number] => 9/679807 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6656 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313501.pdf [firstpage_image] =>[orig_patent_app_number] => 679807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679807
Nonvolatile memory, cell array thereof, and method for sensing data therefrom Oct 4, 2000 Issued
Array ( [id] => 4418516 [patent_doc_number] => 06310805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Architecture for a dual-bank page mode memory with redundancy' [patent_app_type] => 1 [patent_app_number] => 9/676902 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6376 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310805.pdf [firstpage_image] =>[orig_patent_app_number] => 676902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676902
Architecture for a dual-bank page mode memory with redundancy Oct 1, 2000 Issued
Array ( [id] => 4419864 [patent_doc_number] => 06266263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'CAM array with minimum cell size' [patent_app_type] => 1 [patent_app_number] => 9/678502 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 25093 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266263.pdf [firstpage_image] =>[orig_patent_app_number] => 678502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/678502
CAM array with minimum cell size Oct 1, 2000 Issued
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