Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4407219 [patent_doc_number] => 06298002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Memory structures having selectively disabled portions for power conservation' [patent_app_type] => 1 [patent_app_number] => 9/459904 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2706 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298002.pdf [firstpage_image] =>[orig_patent_app_number] => 459904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459904
Memory structures having selectively disabled portions for power conservation Dec 13, 1999 Issued
Array ( [id] => 1531200 [patent_doc_number] => 06480432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Flash memory device having mask ROM cells for self-test' [patent_app_type] => B1 [patent_app_number] => 09/458206 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3374 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480432.pdf [firstpage_image] =>[orig_patent_app_number] => 09458206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458206
Flash memory device having mask ROM cells for self-test Dec 9, 1999 Issued
Array ( [id] => 4273078 [patent_doc_number] => 06205081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Address generating circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/457906 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9845 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205081.pdf [firstpage_image] =>[orig_patent_app_number] => 457906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457906
Address generating circuit of semiconductor memory device Dec 7, 1999 Issued
Array ( [id] => 1410619 [patent_doc_number] => 06545932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'SDRAM and method for data accesses of SDRAM' [patent_app_type] => B1 [patent_app_number] => 09/452408 [patent_app_country] => US [patent_app_date] => 1999-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3121 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545932.pdf [firstpage_image] =>[orig_patent_app_number] => 09452408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452408
SDRAM and method for data accesses of SDRAM Nov 30, 1999 Issued
Array ( [id] => 4102593 [patent_doc_number] => 06134143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Multi-state flash memory defect management' [patent_app_type] => 1 [patent_app_number] => 9/443661 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7931 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134143.pdf [firstpage_image] =>[orig_patent_app_number] => 443661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/443661
Multi-state flash memory defect management Nov 18, 1999 Issued
Array ( [id] => 4231310 [patent_doc_number] => 06088263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Non-volatile memory using substrate electrons' [patent_app_type] => 1 [patent_app_number] => 9/440360 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4410 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088263.pdf [firstpage_image] =>[orig_patent_app_number] => 440360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440360
Non-volatile memory using substrate electrons Nov 14, 1999 Issued
Array ( [id] => 4418611 [patent_doc_number] => 06240007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Nonvolatile ferroelectric memory device having global and local bitlines and split workline driver' [patent_app_type] => 1 [patent_app_number] => 9/432104 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 9846 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240007.pdf [firstpage_image] =>[orig_patent_app_number] => 432104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432104
Nonvolatile ferroelectric memory device having global and local bitlines and split workline driver Nov 1, 1999 Issued
Array ( [id] => 4420070 [patent_doc_number] => 06229744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor memory device with function of equalizing voltage of dataline pair' [patent_app_type] => 1 [patent_app_number] => 9/429402 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2083 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229744.pdf [firstpage_image] =>[orig_patent_app_number] => 429402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429402
Semiconductor memory device with function of equalizing voltage of dataline pair Oct 27, 1999 Issued
Array ( [id] => 4369229 [patent_doc_number] => 06169693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Self-convergence of post-erase threshold voltages in a flash memory cell using transient response' [patent_app_type] => 1 [patent_app_number] => 9/429239 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3990 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169693.pdf [firstpage_image] =>[orig_patent_app_number] => 429239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429239
Self-convergence of post-erase threshold voltages in a flash memory cell using transient response Oct 27, 1999 Issued
Array ( [id] => 4368456 [patent_doc_number] => 06175525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Non-volatile storage latch' [patent_app_type] => 1 [patent_app_number] => 9/429664 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4896 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175525.pdf [firstpage_image] =>[orig_patent_app_number] => 429664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429664
Non-volatile storage latch Oct 27, 1999 Issued
Array ( [id] => 4261704 [patent_doc_number] => 06137724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages' [patent_app_type] => 1 [patent_app_number] => 9/427344 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 7144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137724.pdf [firstpage_image] =>[orig_patent_app_number] => 427344 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427344
Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages Oct 25, 1999 Issued
Array ( [id] => 4418742 [patent_doc_number] => 06240020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/427406 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 30 [patent_no_of_words] => 5418 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240020.pdf [firstpage_image] =>[orig_patent_app_number] => 427406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427406
Method of bitline shielding in conjunction with a precharging scheme for nand-based flash memory devices Oct 24, 1999 Issued
Array ( [id] => 1538640 [patent_doc_number] => 06490213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Crossbar switch and method with crosspoint circuit' [patent_app_type] => B1 [patent_app_number] => 09/419702 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8340 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490213.pdf [firstpage_image] =>[orig_patent_app_number] => 09419702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419702
Crossbar switch and method with crosspoint circuit Oct 13, 1999 Issued
Array ( [id] => 4331334 [patent_doc_number] => 06249468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Semiconductor memory device with switching element for isolating bit lines during testing' [patent_app_type] => 1 [patent_app_number] => 9/412504 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6746 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249468.pdf [firstpage_image] =>[orig_patent_app_number] => 412504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412504
Semiconductor memory device with switching element for isolating bit lines during testing Oct 4, 1999 Issued
Array ( [id] => 7027353 [patent_doc_number] => 20010014049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'APPARATUS AND METHOD FOR THERMAL REGULATION IN MEMORY SUBSYSTEMS' [patent_app_type] => new [patent_app_number] => 09/401988 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7263 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014049.pdf [firstpage_image] =>[orig_patent_app_number] => 09401988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401988
Apparatus and method for thermal regulation in memory subsystems Sep 22, 1999 Issued
Array ( [id] => 4416386 [patent_doc_number] => 06272056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/401502 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 45 [patent_no_of_words] => 21521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272056.pdf [firstpage_image] =>[orig_patent_app_number] => 401502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401502
Semiconductor memory device capable of implementing redundancy-based repair efficiently in relation to layout and operating speed and semiconductor integrated circuit device having such semiconductor memory device Sep 21, 1999 Issued
Array ( [id] => 4145549 [patent_doc_number] => 06147922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Non-volatile storage latch' [patent_app_type] => 1 [patent_app_number] => 9/396189 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5430 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147922.pdf [firstpage_image] =>[orig_patent_app_number] => 396189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396189
Non-volatile storage latch Sep 13, 1999 Issued
Array ( [id] => 4170298 [patent_doc_number] => 06157574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data' [patent_app_type] => 1 [patent_app_number] => 9/394299 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 12522 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157574.pdf [firstpage_image] =>[orig_patent_app_number] => 394299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394299
Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data Sep 9, 1999 Issued
Array ( [id] => 4250808 [patent_doc_number] => 06144611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method for clearing memory contents and memory array capable of performing the same' [patent_app_type] => 1 [patent_app_number] => 9/391904 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3350 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144611.pdf [firstpage_image] =>[orig_patent_app_number] => 391904 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391904
Method for clearing memory contents and memory array capable of performing the same Sep 6, 1999 Issued
Array ( [id] => 4096052 [patent_doc_number] => 06163500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Memory with combined synchronous burst and bus efficient functionality' [patent_app_type] => 1 [patent_app_number] => 9/389313 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163500.pdf [firstpage_image] =>[orig_patent_app_number] => 389313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389313
Memory with combined synchronous burst and bus efficient functionality Sep 1, 1999 Issued
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