Search

Jon D. Epperson

Examiner (ID: 17159)

Most Active Art Unit
1639
Art Unit(s)
6211, 1627, 1639
Total Applications
310
Issued Applications
79
Pending Applications
46
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1546806 [patent_doc_number] => 06373743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Ferroelectric memory and method of operating same' [patent_app_type] => B1 [patent_app_number] => 09/385308 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 16639 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373743.pdf [firstpage_image] =>[orig_patent_app_number] => 09385308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385308
Ferroelectric memory and method of operating same Aug 29, 1999 Issued
Array ( [id] => 4272579 [patent_doc_number] => 06205049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Five-transistor SRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/384300 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205049.pdf [firstpage_image] =>[orig_patent_app_number] => 384300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384300
Five-transistor SRAM cell Aug 25, 1999 Issued
Array ( [id] => 4302419 [patent_doc_number] => 06212099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Preventing data corruption in a memory device using a modified memory cell conditioning methodology' [patent_app_type] => 1 [patent_app_number] => 9/378306 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4400 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212099.pdf [firstpage_image] =>[orig_patent_app_number] => 378306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378306
Preventing data corruption in a memory device using a modified memory cell conditioning methodology Aug 19, 1999 Issued
Array ( [id] => 4418547 [patent_doc_number] => 06240000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Content addressable memory with reduced transient current' [patent_app_type] => 1 [patent_app_number] => 9/376397 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 9626 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240000.pdf [firstpage_image] =>[orig_patent_app_number] => 376397 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376397
Content addressable memory with reduced transient current Aug 17, 1999 Issued
Array ( [id] => 1555954 [patent_doc_number] => 06349061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/375697 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349061.pdf [firstpage_image] =>[orig_patent_app_number] => 09375697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375697
Non-volatile semiconductor memory Aug 16, 1999 Issued
Array ( [id] => 4185169 [patent_doc_number] => 06141246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Memory device with sense amplifier that sets the voltage drop across the cells of the device' [patent_app_type] => 1 [patent_app_number] => 9/373791 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 9710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141246.pdf [firstpage_image] =>[orig_patent_app_number] => 373791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373791
Memory device with sense amplifier that sets the voltage drop across the cells of the device Aug 12, 1999 Issued
Array ( [id] => 4317161 [patent_doc_number] => 06188627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method and system for improving DRAM subsystem performance using burst refresh control' [patent_app_type] => 1 [patent_app_number] => 9/374200 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2485 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188627.pdf [firstpage_image] =>[orig_patent_app_number] => 374200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374200
Method and system for improving DRAM subsystem performance using burst refresh control Aug 12, 1999 Issued
Array ( [id] => 4247103 [patent_doc_number] => 06118691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Memory cell with a Frohmann-Bentchkowsky EPROM memory transistor that reduces the voltage across an unprogrammed memory transistor during a read' [patent_app_type] => 1 [patent_app_number] => 9/374001 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 9412 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118691.pdf [firstpage_image] =>[orig_patent_app_number] => 374001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374001
Memory cell with a Frohmann-Bentchkowsky EPROM memory transistor that reduces the voltage across an unprogrammed memory transistor during a read Aug 12, 1999 Issued
Array ( [id] => 4110998 [patent_doc_number] => 06067273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Semiconductor memory burst length count determination detector' [patent_app_type] => 1 [patent_app_number] => 9/363194 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6190 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067273.pdf [firstpage_image] =>[orig_patent_app_number] => 363194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363194
Semiconductor memory burst length count determination detector Jul 28, 1999 Issued
Array ( [id] => 4170372 [patent_doc_number] => 06157578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method and apparatus for accessing a memory device' [patent_app_type] => 1 [patent_app_number] => 9/354398 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157578.pdf [firstpage_image] =>[orig_patent_app_number] => 354398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354398
Method and apparatus for accessing a memory device Jul 14, 1999 Issued
Array ( [id] => 1450059 [patent_doc_number] => 06370075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Charge pump circuit adjustable in response to an external voltage source' [patent_app_type] => B1 [patent_app_number] => 09/343206 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 54 [patent_no_of_words] => 18947 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370075.pdf [firstpage_image] =>[orig_patent_app_number] => 09343206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343206
Charge pump circuit adjustable in response to an external voltage source Jun 28, 1999 Issued
Array ( [id] => 4170403 [patent_doc_number] => 06104659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Memory device' [patent_app_type] => 1 [patent_app_number] => 9/338599 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5662 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104659.pdf [firstpage_image] =>[orig_patent_app_number] => 338599 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338599
Memory device Jun 22, 1999 Issued
Array ( [id] => 4231351 [patent_doc_number] => 06088266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and apparatus for pulse programming' [patent_app_type] => 1 [patent_app_number] => 9/332488 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2531 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088266.pdf [firstpage_image] =>[orig_patent_app_number] => 332488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/332488
Method and apparatus for pulse programming Jun 13, 1999 Issued
Array ( [id] => 4256772 [patent_doc_number] => 06222380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'High speed parallel/serial link for data communication' [patent_app_type] => 1 [patent_app_number] => 9/330968 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7981 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222380.pdf [firstpage_image] =>[orig_patent_app_number] => 330968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330968
High speed parallel/serial link for data communication Jun 10, 1999 Issued
Array ( [id] => 4357914 [patent_doc_number] => 06215330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Differential diode transistor logic (DDTL) circuit enhancements' [patent_app_type] => 1 [patent_app_number] => 9/330553 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5958 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215330.pdf [firstpage_image] =>[orig_patent_app_number] => 330553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330553
Differential diode transistor logic (DDTL) circuit enhancements Jun 10, 1999 Issued
Array ( [id] => 4414345 [patent_doc_number] => 06239611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Circuit and method for testing whether a programmable logic device complies with a zero-hold-time requirement' [patent_app_type] => 1 [patent_app_number] => 9/329962 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3675 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239611.pdf [firstpage_image] =>[orig_patent_app_number] => 329962 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329962
Circuit and method for testing whether a programmable logic device complies with a zero-hold-time requirement Jun 9, 1999 Issued
Array ( [id] => 4311495 [patent_doc_number] => 06188243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Input/output circuit with high input/output voltage tolerance' [patent_app_type] => 1 [patent_app_number] => 9/329112 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3949 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188243.pdf [firstpage_image] =>[orig_patent_app_number] => 329112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329112
Input/output circuit with high input/output voltage tolerance Jun 8, 1999 Issued
Array ( [id] => 4165008 [patent_doc_number] => 06157217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method of synchronizing computing units connected to one another via a bus system' [patent_app_type] => 1 [patent_app_number] => 9/327695 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2417 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157217.pdf [firstpage_image] =>[orig_patent_app_number] => 327695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327695
Method of synchronizing computing units connected to one another via a bus system Jun 7, 1999 Issued
Array ( [id] => 4191541 [patent_doc_number] => 06150841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Enhanced macrocell module for high density CPLD architectures' [patent_app_type] => 1 [patent_app_number] => 9/326140 [patent_app_country] => US [patent_app_date] => 1999-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 28367 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150841.pdf [firstpage_image] =>[orig_patent_app_number] => 326140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326140
Enhanced macrocell module for high density CPLD architectures Jun 5, 1999 Issued
Array ( [id] => 4415840 [patent_doc_number] => 06265899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Single rail domino logic for four-phase clocking scheme' [patent_app_type] => 1 [patent_app_number] => 9/326161 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3530 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265899.pdf [firstpage_image] =>[orig_patent_app_number] => 326161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326161
Single rail domino logic for four-phase clocking scheme Jun 3, 1999 Issued
Menu