Jon D. Epperson

Array ( [id] => 7063794 [patent_doc_number] => 20010043081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'UNIVERSAL LOGIC CHIP' [patent_app_type] => new [patent_app_number] => 09/326804 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3074 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043081.pdf [firstpage_image] =>[orig_patent_app_number] => 09326804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431675 [patent_doc_number] => 06519754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Methods and apparatuses for designing integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/313225 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 7997 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519754.pdf [firstpage_image] =>[orig_patent_app_number] => 09313225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261656 [patent_doc_number] => 06137721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Memory device having erasable frohmann-bentchkowsky EPROM cells that use a plate-to-floating gate coupled voltage during erasure' [patent_app_type] => 1 [patent_app_number] => 9/301096 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 10319 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137721.pdf [firstpage_image] =>[orig_patent_app_number] => 301096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261688 [patent_doc_number] => 06137723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure' [patent_app_type] => 1 [patent_app_number] => 9/301667 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 9318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137723.pdf [firstpage_image] =>[orig_patent_app_number] => 301667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202073 [patent_doc_number] => 06130840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Memory cell having an erasable Frohmann-Bentchkowsky memory transistor' [patent_app_type] => 1 [patent_app_number] => 9/301097 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 9215 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130840.pdf [firstpage_image] =>[orig_patent_app_number] => 301097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261673 [patent_doc_number] => 06137722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors' [patent_app_type] => 1 [patent_app_number] => 9/301098 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 12579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137722.pdf [firstpage_image] =>[orig_patent_app_number] => 301098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4265984 [patent_doc_number] => 06208558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Acceleration circuit for fast programming and fast chip erase of non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 9/293006 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8329 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208558.pdf [firstpage_image] =>[orig_patent_app_number] => 293006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4209361 [patent_doc_number] => 06014332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Flash memory with adjustable write operation timing' [patent_app_type] => 1 [patent_app_number] => 9/292509 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3213 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014332.pdf [firstpage_image] =>[orig_patent_app_number] => 292509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1402266 [patent_doc_number] => 06552947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Memory tile for use in a tiled memory' [patent_app_type] => B2 [patent_app_number] => 09/286196 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 9476 [patent_no_of_claims] => 244 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552947.pdf [firstpage_image] =>[orig_patent_app_number] => 09286196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4331439 [patent_doc_number] => 06249475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for designing a tiled memory' [patent_app_type] => 1 [patent_app_number] => 9/286186 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 9043 [patent_no_of_claims] => 245 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249475.pdf [firstpage_image] =>[orig_patent_app_number] => 286186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4265931 [patent_doc_number] => 06208555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Negative resistance memory cell and method' [patent_app_type] => 1 [patent_app_number] => 9/281197 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6606 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208555.pdf [firstpage_image] =>[orig_patent_app_number] => 281197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140200 [patent_doc_number] => 06128227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Sense amplifier circuit in a flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/275800 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3449 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128227.pdf [firstpage_image] =>[orig_patent_app_number] => 275800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1452516 [patent_doc_number] => 06370673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method and system for high speed detailed placement of cells within an integrated circuit design' [patent_app_type] => B1 [patent_app_number] => 09/273809 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9323 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370673.pdf [firstpage_image] =>[orig_patent_app_number] => 09273809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114820 [patent_doc_number] => 06052301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/272296 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4988 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052301.pdf [firstpage_image] =>[orig_patent_app_number] => 272296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4191874 [patent_doc_number] => 06038169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Read reference scheme for flash memory' [patent_app_type] => 1 [patent_app_number] => 9/270596 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3862 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038169.pdf [firstpage_image] =>[orig_patent_app_number] => 270596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250655 [patent_doc_number] => 06144600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor memory device having first and second pre-charging circuits' [patent_app_type] => 1 [patent_app_number] => 9/267197 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5839 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144600.pdf [firstpage_image] =>[orig_patent_app_number] => 267197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425588 [patent_doc_number] => 06178133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method and system for accessing rows in multiple memory banks within an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/260197 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16504 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178133.pdf [firstpage_image] =>[orig_patent_app_number] => 260197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102679 [patent_doc_number] => 06134149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and apparatus for reducing high current during chip erase in flash memories' [patent_app_type] => 1 [patent_app_number] => 9/260996 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4939 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134149.pdf [firstpage_image] =>[orig_patent_app_number] => 260996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407078 [patent_doc_number] => 06297989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Applications for non-volatile memory cells' [patent_app_type] => 1 [patent_app_number] => 9/261597 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5758 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297989.pdf [firstpage_image] =>[orig_patent_app_number] => 261597 [rel_patent_id] =>[rel_patent_doc_number] =>)