Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4197166 [patent_doc_number] => 06154055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Programmable logic array integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 9/405556 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12933 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154055.pdf [firstpage_image] =>[orig_patent_app_number] => 405556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405556
Programmable logic array integrated circuit devices Sep 23, 1999 Issued
Array ( [id] => 4366936 [patent_doc_number] => 06191616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Low power, high speed level shifter' [patent_app_type] => 1 [patent_app_number] => 9/371304 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2797 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191616.pdf [firstpage_image] =>[orig_patent_app_number] => 371304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371304
Low power, high speed level shifter Aug 9, 1999 Issued
Array ( [id] => 4303247 [patent_doc_number] => 06184702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Crosstalk prevention circuit' [patent_app_type] => 1 [patent_app_number] => 9/360229 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 7440 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184702.pdf [firstpage_image] =>[orig_patent_app_number] => 360229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360229
Crosstalk prevention circuit Jul 22, 1999 Issued
Array ( [id] => 4104898 [patent_doc_number] => 06049229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder' [patent_app_type] => 1 [patent_app_number] => 9/348092 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5474 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 820 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049229.pdf [firstpage_image] =>[orig_patent_app_number] => 348092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348092
Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder Jul 5, 1999 Issued
Array ( [id] => 4424328 [patent_doc_number] => 06177811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/348623 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 165 [patent_no_of_words] => 44498 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177811.pdf [firstpage_image] =>[orig_patent_app_number] => 348623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348623
Semiconductor integrated circuit device Jul 5, 1999 Issued
Array ( [id] => 4197055 [patent_doc_number] => 06154047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Bus configuration and input/output buffer' [patent_app_type] => 1 [patent_app_number] => 9/339853 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 33 [patent_no_of_words] => 10937 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154047.pdf [firstpage_image] =>[orig_patent_app_number] => 339853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339853
Bus configuration and input/output buffer Jun 24, 1999 Issued
Array ( [id] => 4255635 [patent_doc_number] => 06137312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Voltage level translator' [patent_app_type] => 1 [patent_app_number] => 9/327040 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5291 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137312.pdf [firstpage_image] =>[orig_patent_app_number] => 327040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327040
Voltage level translator Jun 6, 1999 Issued
Array ( [id] => 4191659 [patent_doc_number] => 06150848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication' [patent_app_type] => 1 [patent_app_number] => 9/304583 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6733 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150848.pdf [firstpage_image] =>[orig_patent_app_number] => 304583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304583
Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication May 3, 1999 Issued
Array ( [id] => 4312897 [patent_doc_number] => 06188338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Coding apparatus, decoding apparatus and methods applied thereto' [patent_app_type] => 1 [patent_app_number] => 9/301552 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188338.pdf [firstpage_image] =>[orig_patent_app_number] => 301552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301552
Coding apparatus, decoding apparatus and methods applied thereto Apr 28, 1999 Issued
Array ( [id] => 4364329 [patent_doc_number] => 06175251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Semiconductor integrated circuit device having power reduction' [patent_app_type] => 1 [patent_app_number] => 9/291957 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 59 [patent_no_of_words] => 18604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175251.pdf [firstpage_image] =>[orig_patent_app_number] => 291957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291957
Semiconductor integrated circuit device having power reduction Apr 14, 1999 Issued
Array ( [id] => 4110743 [patent_doc_number] => 06100720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Low dissipation inverter circuit' [patent_app_type] => 1 [patent_app_number] => 9/287582 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3752 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100720.pdf [firstpage_image] =>[orig_patent_app_number] => 287582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287582
Low dissipation inverter circuit Apr 5, 1999 Issued
Array ( [id] => 4134352 [patent_doc_number] => 06127841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'CMOS buffer having stable threshold voltage' [patent_app_type] => 1 [patent_app_number] => 9/276342 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4126 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127841.pdf [firstpage_image] =>[orig_patent_app_number] => 276342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276342
CMOS buffer having stable threshold voltage Mar 24, 1999 Issued
Array ( [id] => 4103933 [patent_doc_number] => 06097213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Switching circuit with an output voltage changing among four possible values' [patent_app_type] => 1 [patent_app_number] => 9/275691 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2608 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097213.pdf [firstpage_image] =>[orig_patent_app_number] => 275691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275691
Switching circuit with an output voltage changing among four possible values Mar 23, 1999 Issued
Array ( [id] => 4192623 [patent_doc_number] => 06094071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Initialization of floating body dynamic circuitry' [patent_app_type] => 1 [patent_app_number] => 9/270188 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2894 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094071.pdf [firstpage_image] =>[orig_patent_app_number] => 270188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270188
Initialization of floating body dynamic circuitry Mar 14, 1999 Issued
Array ( [id] => 4413348 [patent_doc_number] => 06172531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Low power wordline decoder circuit with minimized hold time' [patent_app_type] => 1 [patent_app_number] => 9/251089 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2630 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172531.pdf [firstpage_image] =>[orig_patent_app_number] => 251089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251089
Low power wordline decoder circuit with minimized hold time Feb 15, 1999 Issued
Array ( [id] => 4303275 [patent_doc_number] => 06184704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Design method for compensation of process variation in CMOS digital input circuits' [patent_app_type] => 1 [patent_app_number] => 9/246294 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2165 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184704.pdf [firstpage_image] =>[orig_patent_app_number] => 246294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246294
Design method for compensation of process variation in CMOS digital input circuits Feb 7, 1999 Issued
Array ( [id] => 4104939 [patent_doc_number] => 06049232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/225291 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4626 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049232.pdf [firstpage_image] =>[orig_patent_app_number] => 225291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225291
Semiconductor integrated circuit Jan 4, 1999 Issued
Array ( [id] => 4164841 [patent_doc_number] => 06157206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'On-chip termination' [patent_app_type] => 1 [patent_app_number] => 9/224369 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157206.pdf [firstpage_image] =>[orig_patent_app_number] => 224369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224369
On-chip termination Dec 30, 1998 Issued
Array ( [id] => 4134463 [patent_doc_number] => 06127846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Programmable logic array devices with interconnect lines of various lengths' [patent_app_type] => 1 [patent_app_number] => 9/217771 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4746 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127846.pdf [firstpage_image] =>[orig_patent_app_number] => 217771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217771
Programmable logic array devices with interconnect lines of various lengths Dec 20, 1998 Issued
Array ( [id] => 4184993 [patent_doc_number] => RE036839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method and apparatus for reducing power consumption in digital electronic circuits' [patent_app_type] => 2 [patent_app_number] => 9/212854 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5325 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036839.pdf [firstpage_image] =>[orig_patent_app_number] => 212854 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212854
Method and apparatus for reducing power consumption in digital electronic circuits Dec 15, 1998 Issued
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