Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
08/723925 HIGH VOLTAGE LEVEL SHIFTING CMOS BUFFER Sep 30, 1996 Abandoned
Array ( [id] => 3767398 [patent_doc_number] => 05852373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Static-dynamic logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/723814 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2101 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852373.pdf [firstpage_image] =>[orig_patent_app_number] => 723814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723814
Static-dynamic logic circuit Sep 29, 1996 Issued
Array ( [id] => 3919886 [patent_doc_number] => 06002270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Synchronous differential logic system for hyperfrequency operation' [patent_app_type] => 1 [patent_app_number] => 8/723272 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5501 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002270.pdf [firstpage_image] =>[orig_patent_app_number] => 723272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723272
Synchronous differential logic system for hyperfrequency operation Sep 29, 1996 Issued
Array ( [id] => 3898067 [patent_doc_number] => 05834948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Output circuit' [patent_app_type] => 1 [patent_app_number] => 8/710544 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12930 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834948.pdf [firstpage_image] =>[orig_patent_app_number] => 710544 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710544
Output circuit Sep 18, 1996 Issued
Array ( [id] => 4021358 [patent_doc_number] => 05880604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Semiconductor integrated circuit device having power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 8/714994 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 70 [patent_no_of_words] => 22854 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880604.pdf [firstpage_image] =>[orig_patent_app_number] => 714994 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714994
Semiconductor integrated circuit device having power reduction mechanism Sep 16, 1996 Issued
Array ( [id] => 3784494 [patent_doc_number] => 05818258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Integrated circuit output buffers having duration sensitive output voltage, and related buffering methods' [patent_app_type] => 1 [patent_app_number] => 8/707903 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5313 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818258.pdf [firstpage_image] =>[orig_patent_app_number] => 707903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707903
Integrated circuit output buffers having duration sensitive output voltage, and related buffering methods Sep 11, 1996 Issued
Array ( [id] => 3734365 [patent_doc_number] => 05703498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Programmable array clock/reset resource' [patent_app_type] => 1 [patent_app_number] => 8/709060 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6946 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703498.pdf [firstpage_image] =>[orig_patent_app_number] => 709060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709060
Programmable array clock/reset resource Sep 5, 1996 Issued
Array ( [id] => 3752364 [patent_doc_number] => 05717346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Low skew multiplexer network and programmable array clock/reset application thereof' [patent_app_type] => 1 [patent_app_number] => 8/709074 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6947 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717346.pdf [firstpage_image] =>[orig_patent_app_number] => 709074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709074
Low skew multiplexer network and programmable array clock/reset application thereof Sep 5, 1996 Issued
Array ( [id] => 4139085 [patent_doc_number] => 06034547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method and apparatus for universal program controlled bus' [patent_app_type] => 1 [patent_app_number] => 8/708403 [patent_app_country] => US [patent_app_date] => 1996-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5191 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034547.pdf [firstpage_image] =>[orig_patent_app_number] => 708403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708403
Method and apparatus for universal program controlled bus Sep 3, 1996 Issued
Array ( [id] => 3893296 [patent_doc_number] => 05894231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'High speed bi-MOS logic circuit operative under low power voltage' [patent_app_type] => 1 [patent_app_number] => 8/707431 [patent_app_country] => US [patent_app_date] => 1996-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5227 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894231.pdf [firstpage_image] =>[orig_patent_app_number] => 707431 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707431
High speed bi-MOS logic circuit operative under low power voltage Sep 3, 1996 Issued
Array ( [id] => 3801242 [patent_doc_number] => 05781029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Broadband matching technique for high speed logic and high resolution video signals' [patent_app_type] => 1 [patent_app_number] => 8/706816 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3139 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781029.pdf [firstpage_image] =>[orig_patent_app_number] => 706816 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/706816
Broadband matching technique for high speed logic and high resolution video signals Sep 2, 1996 Issued
Array ( [id] => 4058977 [patent_doc_number] => 05933023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines' [patent_app_type] => 1 [patent_app_number] => 8/708247 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 10083 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933023.pdf [firstpage_image] =>[orig_patent_app_number] => 708247 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708247
FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines Sep 2, 1996 Issued
Array ( [id] => 3803802 [patent_doc_number] => 05828234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Pulsed reset single phase domino logic' [patent_app_type] => 1 [patent_app_number] => 8/702244 [patent_app_country] => US [patent_app_date] => 1996-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5643 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828234.pdf [firstpage_image] =>[orig_patent_app_number] => 702244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702244
Pulsed reset single phase domino logic Aug 26, 1996 Issued
Array ( [id] => 3814425 [patent_doc_number] => 05831448 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Function unit for fine-gained FPGA' [patent_app_type] => 1 [patent_app_number] => 8/708134 [patent_app_country] => US [patent_app_date] => 1996-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 61 [patent_no_of_words] => 27748 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831448.pdf [firstpage_image] =>[orig_patent_app_number] => 708134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708134
Function unit for fine-gained FPGA Aug 26, 1996 Issued
Array ( [id] => 4178839 [patent_doc_number] => 06140835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Input buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/703376 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5096 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140835.pdf [firstpage_image] =>[orig_patent_app_number] => 703376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703376
Input buffer circuit Aug 25, 1996 Issued
Array ( [id] => 4115120 [patent_doc_number] => 06057702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Bus driver' [patent_app_type] => 1 [patent_app_number] => 8/701691 [patent_app_country] => US [patent_app_date] => 1996-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057702.pdf [firstpage_image] =>[orig_patent_app_number] => 701691 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701691
Bus driver Aug 21, 1996 Issued
Array ( [id] => 3803752 [patent_doc_number] => 05828231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'High voltage tolerant input/output circuit' [patent_app_type] => 1 [patent_app_number] => 8/700247 [patent_app_country] => US [patent_app_date] => 1996-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5855 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828231.pdf [firstpage_image] =>[orig_patent_app_number] => 700247 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/700247
High voltage tolerant input/output circuit Aug 19, 1996 Issued
Array ( [id] => 3866969 [patent_doc_number] => 05793226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Data output buffer for multiple power supplies' [patent_app_type] => 1 [patent_app_number] => 8/697088 [patent_app_country] => US [patent_app_date] => 1996-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3090 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793226.pdf [firstpage_image] =>[orig_patent_app_number] => 697088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/697088
Data output buffer for multiple power supplies Aug 18, 1996 Issued
Array ( [id] => 3822856 [patent_doc_number] => 05789937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Impedence self-adjusting driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/702406 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4427 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789937.pdf [firstpage_image] =>[orig_patent_app_number] => 702406 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/702406
Impedence self-adjusting driver circuit Aug 13, 1996 Issued
Array ( [id] => 4040542 [patent_doc_number] => 05942916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/696698 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 8361 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/942/05942916.pdf [firstpage_image] =>[orig_patent_app_number] => 696698 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696698
Logic circuit Aug 13, 1996 Issued
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